The stuff we currently have in the i.MX6q dts file can be reused for
the i.MX6dl variants, so factor out a common dtsi file.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Remove the fixed malloc area size from the defconfig and allow
barebox to calculate the size dynamically.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Upstream has dropped those from the base dtsi, as long as we can't
fully switch to the upstream board DT add the correct alias to the
barebox copy.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
v7: eof whitespace fixes
A Patch for supporting the Terasic DE0 NANO-SoC with barebox.
The pretty similar Socrates Board was taken as a starting point with pulling
in the memory timings/pinmux from
http://rocketboards.org/foswiki/view/Documentation/AtlasSoCCompileHardwareDesign
Signed-off-by: Tim Sander <tim@krieglstein.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since 253fb33 (input: gpio-keys: convert to input framework) the
gpio-buttons are registered with the input framework which has the
side effect that they are activated during boot and no longer have
to be activated manually by activating the input device console.
This reveals that the gpio-button polarities are wrong: The autoboot
is no longer running through since a gpio button press is wrongly
detected.
Fix the polarities in the barebox dts for now to get back a working
board. A proper fix has been sent upstream to the kernel. Once this
has landed and propagated back to barebox this patch can be reverted.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When the kernel load address is chosen by the user/image we need
to check if the kernel needs to relocate itself before decompression.
If that's the case the spacing behind the kernel must allow for this
relocation without overwriting anything placed behind the kernel.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of having the same logic for uImage and zImage types duplicated
in the code, split it out into a separate function. This does not change
the behavior of the calculation.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tabs in kconfig help text will create unwanted indention artefacs when
the help text is scrolled horizontally. Replacing tabs with spaces.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The evaluation boards EDB9302 and Olimex-CS-E9302 both use a
KS8721BL transceiver in default strapping which is phy_addr=1
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Use ARM_USE_COMPRESSED_DTB for all AM335x based board,
to reduce the image size even more.
Saves about 9kB in MLO image and 20kB in barebox image.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reduce even more size of beaglebone MLO device tree with stripping
the clocks.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
use eeprom as name like in the kernel. This is needed if you use the
state framework.
phycard: also fix index, it has address 0x54
Signed-off-by: Jan Remmet <j.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since commit 764ae1647c ("ARM: i.MX: Add correct SoC type detection
for i.MX6") the definition of the function cpu_is_mx6q and cpu_is_mx6dl
has changed. Before that change they match the SoM family Quad/Dual and
DualLite/Solo. After that change they are SoM specific. They match only
Quad and DualLite. There are extra functions cpu_is_mx6d and cpu_is_mx6s
for SoM Dual and Solo.
We have not seen any real world consequences of this problem yet.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since commit 0ff58575c9 ("dts: update to v4.5-rc1") the compatible
"fsl,imx6q-gpt" was removed from imx6dl.dtsi. Now there is only the
Solo/DualLite specific compatible "fsl,imx6dl-gpt". Adapt the driver
for that change.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The cpu_is_mx6* function for the i.MX6 Solo was missing. All other
functions are already defined.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of returning an error when a locked region is read, fill
the result with 0xbadabada to indicate a locked region is read.
This way a md -s /dev/imx-ocotp does not abort when it encounters
locked regions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Throughout our codebase the private context pointer is the first
argument to a function. Do this for the ocotp driver aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Even when the control register has offset 0x0 it's still nice
to use a register define for it. Accessing priv->base directly
just looks wrong.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
All i.MX6 SoCs except the i.MX6SL have 4kbit fuses. The i.MX6SL has
2kbit fuses. Fix the device size accordingly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Pass the config file to cmd_imx_image as arguments to make it more
flexible. Also add the possibility for another arg containing additional
options.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The imx-image tool can now generate signed images itself, so we can
switch to this mechanism:
- Move the CSF templates to header files which can be included by the
flash config files
- remove images/Makefile.imxhabv4 which is no longer necessary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There's not only HABv4 but also HABv3. No need to put the corresponding
code in separate directories, so rename the habv4 directory to hab.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For signing i.MX images with HABv3 we need several certificates. Add
their pathes to Kconfig variables to make them available to the build
system.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This implementation is inspired by U-Boot's FIT support. Instead of
using libfdt (which does not exist in barebox), configuration signatures
are verified by using a simplified DT parser based on barebox's own
code.
Currently, only signed configurations with hashed images are supported,
as the other variants are less useful for verified boot. Compatible FIT
images can be created using U-Boot's mkimage tool.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In barebox the function digest_alloc() allocates a digest based on a string.
When a subsystem already uses an integer value to identify a digest it makes no
sense to create a string and pass it to digest_alloc(), where it is parsed
again. This patch adds the possibility to get a digest by an enum.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The initrd code is distributed in several places in the bootm code.
Move it all together in bootm_load_initrd().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We can make the dryrun option more useful by calling into the handlers.
With this we can detect more cases that can go wrong during boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Setting a fixed memory size prevents from using the different board
variants with different memories equipped.
barebox is able to read RAM size informations from the imx53 RAM
controller and thus does not require this information passed via dts.
Signed-off-by: Enrico Jorns <ejo@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Setup the plls with Master Osc. clock speed from the SYSBOOT
Configuration Pin.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Move the function to read the Master OSC speed from
the SYSBOOT Configuration Pin for reuse.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently only second stage booting from the vendor U-Boot is tested. I
don't want to flash barebox into NAND yet because UART-booting for
recovery doesn't work for me.
Working so far are:
- UART
- networking
- nand flash
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
barebox can be called with the kernel calling convention, so
we can reuse the handler instead of creating a barebox specific
handler.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM do_bootm_linux is not only called with uImages but also with
raw images, so we can't use uimage_get_size() here. Introduce
bootm_get_os_size() which handles the different image types.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Claiming that all of PXA has CLK implemented, while only PXA3XX
selects the relevant clock implementations causes lots of build
failures for the other PXA architectures.
Fix it by moving the HAVE_CLK select to the one PXA arch, that
actually has it.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The lowlevel startup function jumps directly to the main
cluster if we are already running there. This allows for a
significant cleanup of the board startup code by directly
using the FDT address available there.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The gpio-keys driver takes ascii key codes from platform_data and Linux
keycodes from device tree. Convert the ascii keys over to Linux
keycodes to get rid of the special cases in the driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Future additions will make the function too big to live as a static
inline function. Move to a C file and while at it, move matrix_keypad.h
to include/input/ where it belongs to.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Commit 4d70da6 ("ARM: MXS: power-init: Add parameters to
mx28_power_init()") causes imx233-olinuxino to not boot anymore.
imx233-olinuxino is commonly powered from external input supply,
so adjust the mx23_power_init() arguments to reflect that.
Reported-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add code necessary for correct initialization of exception vector
table when MMU is disabled.
Note: Only ARMv7 support is implemented
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add code to make sure that normal vector exception table, when it is
used due to unavailability of the high vector table, was not re-mapped
from 0x0 via VBAR by someone else before us.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
OF fixups cm_cogent_fixup() and hb_fixup() are supposed to modify the
Linux device tree. And they did originally, but commit
e520a8cc46 changed them to use
for_each_compatible_node(), which iterates through the Barebox DT.
Use new for_each_compatible_node_from() to specify the Linux DT root
as the start point.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
socfpga would load the environment from a file named "barebox.env"
located on the device "/dev/mmc0.1". Both those names are hard-coded
in the socfpga code and can't be changed.
Barebox supports selecting the location of the environment using a
"barebox,environment" node in device tree's "chosen" node. And
recently supports specifying that the env should come from a file on
this device.
Change socfpga to use this mechanism by adding the appropriate device
node.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If a new cdev doesn't have a device_node defined when passed to
devfs_create(), set it to the device_node of the parent device, if one
exists.
For non-partitions, like ocotp or eeprom devices, this is the correct
thing to do. Partitions need to use, and do use, a different node.
The code from commit 274e0b8dc4 to set
device_node in ocotp can be removed.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds Raspberry Pi 2 support in barebox. The features should
be the same like the current RPi status in barebox.
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds parts from u-boot code for doing RPi revision detection
and take care about the "warranty bit". I got this bit on my RPi2.
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch change the align of mbox stack resource to 32. The reason is
that I had some experience with bcm2836 and the mbox implementation,
after setting the align to 64(on bcm2836) the issues was gone.
I found these values inside the u-boot implementation, they use 32
(bcm2835) and 64 (bcm2836).
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch changes the most part of mach-bcm2835 to mach-bcm283x. This
prepares to add RPi2 support which is a bcm2836. This patch changes the
Kconfig entry namens to BCM283X for drivers only. These drivers should
working the same in bcm2836.
While updating defconfig I added LED support/trigger option.
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch fix indentation in core.h of mach-bcm2835.
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The xloader boots the 2nd stage barebox from socfpga_barebox_part when
using NOR. But when using MMC it boots from a hardcoded "disk0.1".
Add the mmc device name to the partition description and use it for
mmc booting.
Add an extern declaration of socfpga_barebox_part to the socfpga
header so that a board can change it to use a different partition.
Initialize socfpga_barebox_part to the default value instead of NULL to
avoid the NULL check later.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In commit 8e3ddc13eb the bootm code was
changed to boot barebox using the same calling convention as the
kernel. Which on ARM is to pass three arguments which are zero, an
architecture code, and a params pointer.
A 2nd stage barebox can be booted using lib/bootstrap, which is
different code from bootm. This code just leaves garbage in the first
three parameters and so doesn't follow the convention.
Change it to be compatible with the ARM kernel booting convention.
This just sends a zero for the architecture, since the code for
architectures depends on boot[zmu] and something using bootstrap
wouldn't have those too. And it just passes NULL for the params since
we don't have a way to pass a device tree from the preloader.
All users of bootstrap are ARM based, but the code is in lib so a
non-ARM board might someday make use of it. If the current code would
work for them, then the change here will be ok too.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Silences gcc5 warning:
In file included from arch/arm/mach-omap/gpmc.c:31:0:
arch/arm/mach-omap/include/mach/sys_info.h:93:83:
warning: inline function 'get_sysboot_value' declared but never defined
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Make sure to not run this board specific initcall on any
other board.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
RAMOOPS is a driver that uses a reserved static memory region to store
the data from the last panic or boot. This helps to debug crashes at the
next boot while preserving the boot messages.
To guarantee a memory area that is not altered by barebox or the kernel,
this area is located at the end of the RAM right after barebox and
before the STACK. This ensures that changing barebox sizes do not
interfere with RAMOOPS.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This helps to understand and find problems with the memory layout of
barebox. It adds another entry for the board data that barebox
allocated.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The memory calculations used are all hardcoded into three different
files, start-pbl.c, uncompress.c and start.c. To make this more readable
and reliable, this patch gathers these information in barebox-arm.h with
static inline functions for the calculation of the memory offsets.
This patch also adds proper handling of different barebox/board data
sizes. Currently only 1MB+Alignment of RAM is reserved for Barebox and
board data. This could be too small for bigger devicetrees and barebox.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
DIV_ROUND_UP is defined in include/linux/kernel.h. Use that instead.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In order for cdev_by_device_node() to be able to return approprate
character device for <&ocotp> phandle cdev->device_node needs to be
initialized with dev->device_node. This patche takes care of that
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Both lubbock and mainstone suspend to RAM were broken by the same
typo. The linux kernel saves the resume address to PSPR, ie. the scratch
pad register, while it was PSSR which was checked in barebox.
Fixing this typo was tested on mainstone where resume from S3 works.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In commit 104a6a7ccf support was added
for Thumb2. It added do_execute() as a way to provide arch dependent
calling veneers for use in "go" and thumb2_execute() as the thumb2 to
arm veneer.
But thumb2_execute() isn't necessary as gcc generates a proper calling
sequence from a standard function pointer call. Thumb2 barebox is
compiled with the AAPCS ABI which requires this.
It also had a bug and didn't pass the arguments properly, but code
execute via "go" rarely uses arguments so this wasn't very noticeable.
Since thumb2 was always the only user of do_execute(), go ahead and
delete that too.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The asm code to do the actual call into the kernel (or another
barebox) when compiled in thumb2 mode isn't necessary. gcc generates
a perfectly good calling sequence from a normal function pointer call.
If it didn't, the code in bootstrap_boot() that uses a function
pointer to jump to the 2nd stage barebox from an xloader wouldn't
work.
It appears to be allowed that the call to kernel() could return, as
neither start_linux() nor kernel() are marked noreturn, and there is
code after calls to start_linux().
The asm code has a bug in this case, as it uses bx and not blx, and
thus doesn't set the link register. Since it's a tail call, this
would be okay, but only if the LR value from the start of
start_linux() (and the callee-saved registers) are restored
beforehand, which isn't done. The gcc generated call sequence will do
this.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
OTG and HOST port are tested with a mass storage device.
Signed-off-by: Florian Vallee <fvallee@eukrea.fr>
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The clocks for the LVDS display bridge have a fixed /3.5 and a
configurable /1,/2 divider in their path. The configurable divider has
to be explicitly configured for single/dual channel support, so we can't
rely on clock rate parent propagation here. Clear the
CLK_SET_RATE_PARENT flag for the configurable divider and configure the
clock explicitly in the ldb driver.
Tested on a custom i.MX6 board, currently untested on i.MX53.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Also move the initcall to the level matching the name of the
function.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With a common clock provided for NAND controller, get rid of the
mach/clock.h way of getting the NAND clock.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a clock with clk_add_physbase for the NAND flash controller on
Zylonite board.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP,
prepare to provide a common clock for the NAND driver on PXA3xx.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since there is no OF support in the xloader on socfpga it uses the
platform_data system. There needs to be a way to supply the
equivalent of the DT property bus-width this way to support devices
that need to use a smaller bus.
So that we don't need to put every flag that might get added to the
MMC_CAP list into platform_data, just put the bus width ones into
platform_data.
The socfpga dts sources specify a bus-width of 4 so use that in the
platform_data for socfpga.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The commit ea1fb2f75d by Eric Nelson
imx6-mmdc: fix automatic power down enable in write level calibration
fixed the incorrect usage of the MAPSR register, but there is one more
place where the MAPSR is misused in the exact same way, so fix that as
well.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
remap_range takes generic MAP_CACHED/MAP_UNCACHED flags which are then
translated into the corresponding ARM specific bits. We call remap_range
internally from dma_alloc_* aswell, but instead of passing the generic
flags we pass the ARM specific bits.
Fix this by creating an internal __remap_range function which takes the
ARM specific bits and use it where appropriate.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The clock driver will overwrite those values anyway, so no
point in setting them in the DCD.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
A comment in the socfpga init said that it was "Clearing emac0 PHY
interface select to 0", but this was doubly incorrect. It was setting
physel for emac1, not emac0, and it was setting physel to 1 (RGMII)
not 0 (GMII). All supported socfpga boards use RGMII, and use emac1,
so fix the comment to reflect the code. But then extend the code to
set the physel for both emac0 and emac1, so it can work on boards that
use either or both emacs (which are called gmac0/1 in the dts).
The Cyclone V datasheet, page 17-60 "EMAC HPS Interface
Initialization", says to set physel while the EMAC is in reset. So
place the EMAC in reset while changing physel. The emacs are not in
reset as code earlier in the boot has already taken most of the
modules out of reset. So put them back in reset while the physel is
changed. The Linux kernel does it this way too.
If barebox has no network support, there is not much point in
configuring the emac physel lines. This would be the case for the
xloader pre-bootloader config, which configures physel, doesn't use
the network, loads the main barebox, which then reconfigures physel
again. Make this code depend on CONFIG_NET so it's just done in the
main barebox. The Linux kernel does not need barebox to do this
initialization to use networking.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current code tests if a partition (i.e. disk0.0) exists and instead
of mounting boot from this partition it uses the whole device (disk0).
This only works because the the FAT code accepts a MBR as input and
automatically skips it.
Let the code use the partition to mount /boot instead as it was
intended. We don't have to stat() the partition device, since this
error will be caught by mount() anyway, so remove the unnecessary
stat().
Reported-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To be able to use dump_stack() without support exception handling the
definition of dump_stack has to move to a file that is actually compiled
without ARM_EXCEPTIONS.
Fixes: d332597c7c ("ARM: make exception handling optional")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for phyFLEX-i.MX6 DualLite 1GiB on one bank with NOR.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for phyFLEX-i.MX6 Solo with 128MB and 256MB RAM on one
memory bank.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for phyFLEX-i.MX6 Quad 512MiB RAM on one bank.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In the current naming schema the phyFLEX-i.MX6 variants which only use
one bank for memory have the suffix "1bank". The variants which use two
banks of memory have no suffix.
The patch fixes the name of the phyFLEX-i.MX6 Solo variant with 512MiB
on one bank. So the name of the image file changes from
barebox-phytec-pbab01s-512mb.img
barebox-phytec-phyboard-subra-512mb.img
to
barebox-phytec-pbab01s-512mb-1bank.img
barebox-phytec-phyboard-subra-512mb-1bank.img
This patch touches the phyFLEX-i.MX6 Kit variant and the
phyBOARD-SUBRA-i.MX6 which shares the same phyFLEX-i.MX6 module.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Rename sd-ext3 to mmc, remove filesystem type from bootargs and remove
bootargs-ip. Add init script 'bootsource' to set boot source priority
and bootscript 'spi' for SPI NOR.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The loadaddr in the flash-headers for the phyFLEX/phyCARD-i.MX6 was set
to 0x20000000 (512MiB). The start of the DDR memory in CPU's memory map
is 0x10000000 (256MiB). So the ROM loader loads the barebox image at the
memory position 256MiB and higher in the DDR memory.
This is a problem when the module doesn't have more than 256MiB of
memory. Therefore the loadaddr is set to the start of the DDR memory.
The patch was tested on a phyFLEX-i.MX6 Quad with 1GiB RAM on one bank
and on a phyCARD-i.MX6 Quad 1GiB RAM on two banks.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The main idea behind this patch is to avoid redundant code. Because of
the module similarities of all i.MX6 based phytec boards, we can merge
its code.
The phytec-som-imx6 merges the code of all i.MX6 based phytec SOMs. So
we will have only one "board" in the barebox for phyCARD-i.MX6 and
phyFLEX-i.MX6.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Use numeric suffix for 'environment-sd3' in device tree. This patch
prepares phytec-phycard-imx6 for the SOM unification.
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The production models have the MAC fuses blown, so we can use a
real MAC address instead of a random one.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The pre-production modules had an external crystal to generate the PHY
reference clock. Production modules rely on the i.MX6 to output the
correct clock.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now that we have a full set of DRAM configuration entries we can
build images for the full set of modules on Hummingboard.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is a complete set of DRAM configuration values for all of the
MicroSOM variants extracted from SolidRun U-Boot.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To reflect that the current image is in fact for a combination of a
MicroSOM i1 with a Hummingboard baseboard.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
No need to carry this cruft around. It's not needed anymore.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Simplify booter update with barebox_update command using special
IMX6 MMC BBU handler.
Signed-off-by: Anton Bondarenko <anton.bondarenko.sama@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On these systems, the base arch has code to load the in flash
environment from a file located in a FAT filesystem. This was
controlled by the config option DEFAULT_ENVIRONMENT. However, that
option turns on compiling the env into the barebox binary itself, as a
backup if the in flash env can't be loaded.
Most other boards have in flash env support unconditionally. But omap
and socfpga also have xloader configurations, which aren't supposed to
have environment support, either in flash or compiled in. If the in
flash env code were unconditional, then the xloaders would gain it.
So the code depends on ENV_HANDLING, which is only set on those boards
that are supposed to have an in flash env and not set on all the
boards that aren't supposed to have it.
If someone wanted to create a board that did have a saved env, but
used an alternate to this generic omap/socfpga file in FAT method,
then they'd probably want to create a new config option to control
this code and have it not be enabled for their board.
Signed-off-by: Trent Piepho <tpiepho@kymetacorp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The phyCORE-AM335x has a SMSC phy mounted. Enabled the driver for it.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There are phyFLEX modules with only the first eth phy mounted.
As barebox only supports the first interface anyway, disable
the second interface for now.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
remap_range is for remapping regions with different cache attributes.
It is implemented for ARM and PowerPC only, the other architectures only
provide stubs.
Currently the new cache attributes are passed in an architecture specific
way and the attributes have to be retrieved by calls to
mmu_get_pte_cached_flags() and mmu_get_pte_uncached_flags().
Make this simpler by providing architecture independent flags which can
be directly passed to remap_range()
Also provide a MAP_ARCH_DEFAULT flag and a arch_can_remap() function.
The MAP_ARCH_DEFAULT defaults to whatever caching type the architecture
has as default. the arch_can_remap() function returns true if the
architecture can change the cache attributes, false otherwise. This
allows the memtest code to better find out what it has to do.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
All versions of barebox_arm_entry (in uncompress.c, start.c and
start-pbl.c) appear to be doing exacty the same thing. So move the
definition into a separate file and use IS_ENABLED macro to avoid
re-definition.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Both barebox_boarddata and barebox_boot_dtb perform essentially the
same function -- hold a pointer to a chunk of private data. Since only
one variable is ever used at any given time we may as well merge those
two variable into one. This also allows us to share more code between
two boot paths (board data vs. device tree)
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add semihosting API implementation and implement a filesystem driver
to access debugging host filesystem using it.
Tested on Freescale SabreSD board (i.MX6Q) using OpenOCD
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Make sure that the DT passed to Linux reflects the actual number of CPU
cores present in the system by reading the SCU configuration. As both
the Q and DL variants of the MX6 have versions with cores fused away,
but the DTs have the maximum number of cores specified, this just deletes
any nonexistent CPU core nodes.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support support for the i.MX6 Technexion Wandboard. The
board comes in different SoC variants and different amounts of RAM.
The baord type is autodetected based on the SoC type, so all boards
can be supported by the same binary image.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Otherwise boards cannot include board files from the kernel dts
without getting the file ordering wrong.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In the current multi image build process the DTBs end up uncompressed
in the PBL. This can be annoying because the PBL is often very size
constrained.
This patch allows to put the DTBs in as lzo compressed binary into
the PBL. Since lzo offers quite good compression ratios for DTBs no
other compression algorithm has been implemented for now.
Boards which want to use the compressed DTBs only have to change
the __dtb_ prefix in the DTB name to __dtb_z_. Also they should select
ARM_USE_COMPRESSED_DTB to make sure barebox supports uncompressing
the DTB.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX6 DL/S DT has been changed to use more specific compatibles as
GPTv2 has a different programming model for modes used in Linux. This
difference doesn't matter for Barebox, but the old mx31 compatible has
been dropped from the DT, so we need to match on the one still present.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Bit 0 of the MAPSR register controls auto power down.
Explicitly clear this bit instead of reserved bit when
exiting from mmdc_do_write_level_calibration().
Signed-off-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The BINARY files given in the config files are expected to be relative
to the place kwbimage is called from. This is bad since it breaks where
kwbimage is called from the build directory and not the source
directory.
It makes more sense to make the paths in the config files relative
to the config files which works with out of tree builds and is also
more what a user normally expects.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
From reading ARM architecture related documentation if appears that
while unaligned memory access is supported by the processor in general
it is not supported if MMU is disabled.
The problem in question can be easily reproduced by building the code
without this patch, MMU disabled, and trying to run 'memtest'
command. Which would in turn call mem_test() which would eventually
call show_progress(). That last function, if build without
-mno-unaligned-access would result in unaligned memory access which
would result in Barebox hanging.
This patch instructs the compiler to not generate any unaligned
accesses to memory thus avoiding the problem.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In order to make the system compliant to the ARMv7 ARM RevC clarifications
regarding conflicting memory aliases the shared override bit needs to be
set. This needs to be done in the bootloader, as the kernel will not apply
any modifications to the AUX_CTRL register by default, as it is a secure only
register.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of using a redundant definition. This makes things a bit cleaner
and also avoids to introduce another private define in the next patch.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There are systems like the Calxeda Highbank, which need to do SMC
calls in order to access the secure L2C registers, which means they
want to replace the outer cache disable function with their own.
As the cache flush before entering the boot target is still needed
and to avoid exposing L2C internals to the architectures move the
flush before disable into the only current user.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
A first stage bootloader can read fat and ext4 filesystems, and
even both can be compiled-in at the same time.
But then xload has a hardcoded fat filesystem mount option which
renders ext4 unusable.
This patch tries to mount it as ext4 if the fat attempt fails.
Then, a typical use case of an ext4 formatted filesystem
is it to be a standard linux filesystem, which contains
boot-related files in /boot. So, when searching for the second stage
bootloader, try /boot/barebox.bin after not finding it in /barebox.bin
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ROM base address in the 9x5 processors lives at 1M, not 4M,
where SMD is, as defined later in the same file.
The ROM includes some tables that are used to build error-correction data
for NAND memory. By using the wrong address, we get wrong data and
the result is undetected bit flips (data at 0x408000 is all zeroes).
Thus, even though our kernel was fixing bit errors in NAND, barebox
was not fixing them. With UBI (our situation) we got I/O errors because
the checksum verification for data nodes failed.
Using the proper address corrects the problem: barebox reports a
"bitflip" message, consistent with the kernel message for the same
file, and the files are properly loaded and booted.
Note: the kernel has the same wrong define, but then the magic number
0x00108000 as spelled in arch/arm/boot/dts/at91sam9x5.dtsi is used
instead of the symbolic name.
Signed-off-by: Edoardo Scaglia <scaglia@amelchem.com>
Signed-off-by: Federico Braghiroli <braghiroli@amelchem.com>
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The backlight enable gpio is in both the ldb node and the panel node.
Remove it from the ldb node where is was unused and fix the polarity
in the panel node. Also make the panel compatible to simple-panel to
let the driver match it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this can be useful on the evaluation board but we don't want
the sequence to launch on custom board when there is not the
switch button on gpio 82
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
OTG and HOST port are tested with a mass storage device.
Signed-off-by: Florian Vallee <fvallee@eukrea.fr>
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
we need to disable second SD chip select properly else the SDRAM size
detection will detect it but there is no memory connected so the boot
will fail
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Florian Vallee <fvallee@eukrea.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
barebox uses 4KiB pages so that number of PTEs is 'size >> 12', not
'size >> 10'.
Thie 'size >> 10' limit is not an immediate problem because it allocates
too much PTEs only which are not used. But it can overflow an integer
multiplication ('i * PAGE_SIZE') which causes undefined behaviour with
gcc5.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
dma_flush_range() expects an address as second argument, not a size.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This fixes build failures in builds without MMU support by providing
a fallback implementation.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch disables the clocks in the Phytec am335x MLOs and reduce the MLO
size by 9kb.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Register the eMMC MLO handler to the barebox_update command.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With this patch the barebox_update command will be extended by the possibility
to flash the MLO to eMMC devices.
The MLO will be flashed to the following addresses:
0x00000
0x20000
0x40000
0x60000
Because the first 512 Bytes of the MLO are reserved for the CHSETTINGS header
and this only use ~80 Bytes, there is space for the partition table in the
header.
The command will overwrite the bootstrap code area and will hold the
partition table and the Boot signature.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
arm_ignore_data_abort can be set to nonzero to ignore data aborts. The
default should be not to ignore data aborts. Fix this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We can now directly point to the partitions in the barebox,environment
binding. Convert some boards over to it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Make sure that the initcall only executes on the expected board.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This replaces the reset_cpu() function which every SoC or board must
provide with registered handlers. This makes it possible to have multiple
reset functions for boards which have multiple ways to reset the machine.
Also boards which have no way at all to reset the machine no longer
have to provide a dummy reset_cpu() function.
The problem this solves is that some machines have external PMICs or
similar to reset the system which have to be preferred over the
internal SoC reset, because the PMIC can reset not only the SoC but also
the external devices.
To pick the right way to reset a machine each handler has a priority. The
default priority is 100 and all currently existing restart handlers are
registered with this priority. of_get_restart_priority() allows to retrieve
the priority from the device tree which makes it possible for boards to
give certain restart handlers a higher priority in order to use this one
instead of the default one.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The pin SD4_DAT4 until SD4_DAT7 are used as revison control.
The pins will be internally pulled up so we read a 1111 for revison 1.
For revison two the first pin (bit) is pulled down (see schematic pfla-02
page 4 "SDIO, NAND-Flash".
On Module rev 1 the pins are connected to the NAND but we have only 8bit NAND
also the i.MX6 only can handle 8bit NAND flashs.
Revisions:
Rev 1: 0xF
Rev 2: 0xE
.
.
.
Rev 15: 0x1
Rev 16: 0x0
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
SoCFPGA is completely multi-image enabled and probes the barebox
from a built-in DT, so there is no point in building a barebox
image that isn't able to probe from DT.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add the missing stdout-path properties for the socfpga boards and
enable CONFIG_CONSOLE_ACTIVATE_NONE.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since we no longer have custom gpio function prototypes we can
drop the prototypes from asm-generic/gpio.h can add them to
include/gpio.h instead. While at it add static inline dummy wrappers
for !CONFIG_GENERIC_GPIO so that code using gpios can compile without
gpio support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Convert zylonite board to the generic environment, and make consistent
with lubbock and mainstone boards.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of using internal devicetree files, use the official ones from
/dts/src/arm.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
i.MX6 is fully DT enabled and the already selected
COMMON_CLK_OF_PROVIDER needs OFTREE support to build properly.
Fixes:
arch/arm/mach-imx/clk-imx6.c: In function 'imx6_ccm_probe':
arch/arm/mach-imx/clk-imx6.c:500:2: error:
invalid use of undefined type 'struct clk_onecell_data'
arch/arm/mach-imx/clk-imx6.c:502:2: error:
implicit declaration of function 'of_clk_add_provider'
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Align with the mainline device tree, include it,
and remove all unchanged nodes and properties.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Align with the mainline device tree, include it,
and remove all unchanged nodes and properties.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
PXA is the only architecture that uses its own prototypes for
the gpio functions because it uses static inline variants of
these functions. For the sake of streamlining with other architectures
move them to a C file and use the generic gpio prototypes.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The files flash-header-*.imxfg contains two defines which are use in
include files flash-header-phytec-*.h. The first define is SETUP_MDCFG0.
In the second define name some RAM size value were used, e.g.
SETUP_S_DL_512MB_1GB or SETUP_1GIB_2GIB_4GIB.
It's better to name also the second define after the register names,
here MMDC1_MDCTL and MMDC1_MDASP, because these values changes for every
RAM configurations and it's consistent with the first define.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Barebox currently names the SPI NOR device "/dev/sst25vf016b",
but the barebox update handler still points to "/dev/m25p80",
causing barebox_update to fail.
Choose a descriptive name instead.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
for bank2_size get_ram_size must be called with the CS1 area. With the
recent fix to calculate CS1 start this now starts at 0x90000000 and no
longer at 0x80000000.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
DDR_64BIT_2GB corresponds to two chip selects (ncs = 2) with 1GiB
each. In this case cs_density must be configured to 8Gb (1GiB).
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current calculation does not take the 0x10000000 offset where
SDRAM starts into account. For example with a 1GiB chip density
the current code calculates cs1 start to 0x40000000, but it
has to be 0x10000000 + 0x40000000 = 0x50000000. Add the missing
8 32MiB chunks.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The cm-fx6 board is a module from Compulab with different i.MX6 SoCs.
This module is also found in the Utilite Mini Computer this patch
also adds support for.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We have functions to setup the i.MX uart for early use, but these all
depend on DEBUG_LL. Move them to imx-uart.h to make them usable for
the regular PBL console.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Several i.MX6 boards like to do their SDRAM setup in code rather than
in DCD tables. Add the SDRAM setup code from U-Boot to make it easy
to adopt the SDRAM setup from the U-Boot port of these boards.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Avoids a build failure if the config does not include ULPI support.
This is similar to what has been done to the PCA100 board.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The variable partname is used in the error path for debugging.
We have to free it after this use.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
AT91 has a custom barebox head that doesn't support Thumb2.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current supported Rockchip board is initialized from a
builtin DTB and I suppose all future boards will do the same.
Fixes various missing functions and prototypes in Rockchip clk
driver.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
So we can drop it from the defconfig and stop bothering
the user with this choice by default.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Explain the relationship between the OCOTP addresses from the i.MX6
Reference Manual and the file offset in '/dev/imx-ocotp'.
Signed-off-by: Stefan Christ <s.christ@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The 32KHz from dmtimer0 is derived from a SoC internal RC oscillator
which is quite inaccurate. Switch to dmtimer2 which is driven from
the high frequency oscillator clock.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for all possible combinations of phyFLEX-AM335x modules.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for all possible combinations of phyCORE-AM335x
modules.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Added support for IM8G16D3FBBG15EI 1024MiB RAM on one chip.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Only enable eeprom when populated. So disable it in dtsi
file and enable if needed in board dts.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current cpu_is_mx6x() functions need the imx6_cpu_type variable
which make them unsuitable for PBL. Add a set of cpu_mx6_is_mx6x()
functions which can be called from PBL aswell. Unlike the cpu_is_mx6x()
functions the cpu_mx6_is_mx6x() functions assume that they are called on
i.MX6 only.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As boot.c now contains code for the pbl compile compile it there
awell. While at it move esdctl.c to obj-pbl-y.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In the pbl the regular bootsource_get cannot be used. Add a function
which returns the bootsource directly with values from the hardware.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a i.MX6 specific entry function which automatically detects the SDRAM
size. The prototype has already been present, but it was never implemented.
Rename it to imx6q_ since the other variants need other functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
Lucas Stach
Tim Sander
Teresa Remmet
Lucas Stach
Alexander Kurz
Arnd Beuscher
Jan Remmet
Wadim Egorov
Stefan Christ
Steffen Trumtrar
Jan Luebbe
Enrico Jorns
Daniel Schultz
Uwe Kleine-König
Philipp Zabel
Fabio Estevam
Andrey Smirnov
Trent Piepho
Alexander Aring
Andrey Panov
Markus Pargmann
Robert Jarzmik
Florian Vallee
Sebastian Hesselbarth
Marek Vasut
Christian Hemp
Uwe Kleine-König
Anton Bondarenko
Michael Grzeschik
Eric Nelson
Vicente Bergas
Edoardo Scaglia
Eric Bénard
Enrico Scholz