The i.MX27/31 have the second chip select enabled by reset default.
This can be considered as a hardware bug, because even boards which
need this settings cannot work out of reset because of the missing
initialization sequence. Detect this reset default setting and disable
this chipselect then to be able to properly detect the SDRAM size.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch provides a global cleanup barebox Kconfig files. This includes
replacing spaces to tabs, formatting in accordance format, removing
extraneous lines and spaces. No functional changes.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for the Garz+Fricke Vincell board. This has
a i.MX53 Processor with 512MB of DDR3 RAM.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for initializing DDR3 RAMs on the i.MX53 type
SDRAM controller. The code automatically detects size/layout of
the connected RAM, detects the bus width and which chipselects are
populated.
While I believe this code is not 100% generic, it is far too
sophisticated to stay in a single board directory. I'm sure
other boards could make use of this aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The pll setup function is exported, so it makes sense to export
the convenience wrappers for specific frequencies aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some boards do not have a DCD table since they initialize everything
in code, so allow to skip it and leave the corresponding pointers
empty.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The code initializing the SDRAM controller is not at the same
place where SDRAM is registered with barebox. To reduce the
risk of registering wrong SDRAM sizes this patch adds a
driver for the ESDCTL which reads back the configured SDRAM
size and registers the memory found with barebox.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In recent reference manuals the plls were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ethernet PLL has a fixed frequency of 500MHz. What is adjustable
are additional dividers which we better describe separately.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds lowlevel debug functions for i.MX. As we have a great variety
of different UARTs on i.MX currently no Kconfig support for chosing the
correct one is added. Instead we expect the user to add the correct
define and issue a compiler warning if he hasn't.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Pass the buffer size to the file detection code. This makes sure we do not
read past the buffer. This is especially useful for ext filesystem detection
as the magic is at byte offset 1080. Also introduce a FILE_TYPE_SAFE_BUFSIZE
define which is set to the minimum bufsize the detection code needs to detect
all known filetypes.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Update help info, it's slightly out of date, and a grammatical fix.
No functional change.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch sets HPM (Host power mask bit) to bit 16 according to i.MX
Reference Manual. Falsely it was set to bit 8, but this controls pull-up
Impedance.
Reported-by: Michael Burkey <mdburkey@gmail.com>
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The same issue was fixed in the Linux kernel in commit
66ddfc6 (mx35: add a missing comma in a pad definition)
for 2.6.33-rc7.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for an update handler for internal boot. Currently
handled are:
- v1 MMC/SD
- v2 MMC/SD
- v2 NAND
where v1 is found on i.MX25, i.MX35 and i.MX51. v2 is found on i.MX53.
This code intentionally does not use the DCD data compiled into every
i.MX internal boot image. This makes it possible to make a pure second
stage barebox bootable on i.MX internal boot devices later.
This has been tested on the i.MX51 babbage, i.MX53 loco and i.MX53 tx53
board.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The KARO Tx53 board in the revision 8030 has an instable SDRAM
setup. It works as long as the MMU is disabled, but the board
crashes at arbitrary places once the MMU gets enabled. So we
need the PLL setup early. Enable it for pbl.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
Alexander Shiyan
Christian Kapeller
Robert P. J. Day
Christoph Fritz
Uwe Kleine-König