This solves a problem which causes boot failure when using a uImage with
device tree. It should also speed up boot because the kernel can skip
copying itself out of the way.
Signed-off-by: Jan Luebbe <jluebbe@debian.org>
The partition layout is board-specific, so only the barebox partitions
need to be in the fixed location expected by the MLO code.
Signed-off-by: Jan Luebbe <jluebbe@debian.org>
We need to wait some time between activating the ethernet and
being able to send the first frame. I have not investigated why
that is the case.
Fixes: SYS#488
As this is the bootm image handler implementation for the kwbootimage
it is of no use if BOOTM is missing and fails to link.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The instructions used in those files are only supported on ARMv7.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The wdog1 pinctrl got fixed with linux upstream commit 213e51ca8df1 ("ARM:
dts: imx7: Add "LPSR" to LPSR iomux pin names").
Remove the old workaround, since it triggers a build error.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
fsl,imx7d-iomuxc is provided by selecting PINCTRL_IMX_IOMUX_V3. Select it
since a system without it will not be very usefull.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As stated in the routine's description this routine is to return void,
hence fix its declaration to remove compiler warning.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Move PIT driver code to 'drivers/clocsource' and accomodate it by
adjusting Kconfig variables. Rename the file to 'timer-atmel-pit.c' to
re-align the driver with code in Linux kernel.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
if not set, barebox will use first console by default.
On this board first console is KEYBOARD_GPIO, so we will end
in unusable state.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The CPU write buffer needs to be coherent with the cache, otherwise
we might flush stale entries with the actual data stuck in the cache.
This is really important on newer CPU core with bigger write buffers.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other parts
(including the cache handling) is still at v6. As we don't make use of
the more advanced features of the v7 MMU in Barebox, it's okay to just
override this to properly identify the CPU as ARMv6.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On ARMv7 the exception vectors inside the barebox binary are used directly
by remapping the vectors base through the VBAR register. While VBAR allows
to remap the exception vectors freely, it still imposes a minimum alignment
of 32 byte, as the lower bits are treated as the exception vector offset.
Enforce this alignment inside the barebox binary.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is necessary to make second stage booting work when the register
window is already moved.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
This just starts the main image of the mvebu image assuming that the
header images just setup the RAM. The position of the internal register
window is provided in the header as introduced in the previous commit.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
A problem when using 2nd stage booting on mvebu is that the first bootloader
already switched the register window location from 0xd0000000 to
0xf1000000 by writing to 0xd0000080. When the second bootloader also
tries to do this switch it writes to the wrong location resulting in an
exception and so a boot failure.
For this reason the base address of the register window is passed in the
barebox header and picked up from there by early code. In a further
patch bootm is taught to put the actual position of the window there for
the second bootloader to finally make second stage booting work.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
binary.0 sets up all RAM but the address decoding isn't adapted accordingly
which makes barebox assume that there are only 512 MiB of RAM on a single
bank instead of two banks with 1 GiB each.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Similar to the two previous commits, this gets rid of a of-fixup which
is strange because the soc init stuff is rerun then when a new dt for
booting into Linux is loaded.
The initcall must be postponed to post-core to ensure
of_machine_is_compatible is working correctly.
The call to mvebu_mbus_add_range is moved to drivers/bus/mvebu-mbus.c to
ensure it's registered early enough.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>