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barebox
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Merge branch 'for-next/imx' 

Conflicts:
	arch/arm/configs/tx25stk5_defconfig
This commit is contained in:
Sascha Hauer 2014-06-04 21:01:40 +02:00
parent 1022dfecfb 999802c14a
commit 6ec2780419
62 changed files with 837 additions and 3109 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boards/boundarydevices-nitrogen6x/board.c
View File

@ -27,7 +27,7 @@ static int nitrogen6x_devices_init(void)
return 0;
imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0);
BBU_HANDLER_FLAG_DEFAULT);
return 0;
}

5
arch/arm/boards/datamodul-edm-qmx6/board.c
View File

@ -104,9 +104,8 @@ static int realq7_env_init(void)
return 0;
imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0x00907000);
imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc3.barebox",
0, NULL, 0, 0x00907000);
BBU_HANDLER_FLAG_DEFAULT);
imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc3.barebox", 0);
return 0;
}
late_initcall(realq7_env_init);

4
arch/arm/boards/dfi-fs700-m60/board.c
View File

@ -111,9 +111,9 @@ static int dfi_fs700_m60_init(void)
flag_mmc |= BBU_HANDLER_FLAG_DEFAULT;
imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc3.boot0",
flag_mmc, NULL, 0, 0);
flag_mmc);
imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0",
flag_spi, NULL, 0, 0);
flag_spi);
armlinux_set_architecture(MACH_TYPE_MX6Q_SABRESD);

8
arch/arm/boards/efika-mx-smartbook/board.c
View File

@ -238,9 +238,6 @@ static struct gpio_led leds[] = {
},
};
extern char flash_header_imx51_genesi_efikasb_start[];
extern char flash_header_imx51_genesi_efikasb_end[];
static int efikamx_late_init(void)
{
int i;
@ -258,10 +255,7 @@ static int efikamx_late_init(void)
writew(0x0, MX51_WDOG_BASE_ADDR + 0x8);
imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc1",
BBU_HANDLER_FLAG_DEFAULT,
(void *)flash_header_imx51_genesi_efikasb_start,
flash_header_imx51_genesi_efikasb_end -
flash_header_imx51_genesi_efikasb_start, 0);
BBU_HANDLER_FLAG_DEFAULT);
armlinux_set_architecture(2370);
armlinux_set_revision(0x5100 | imx_silicon_revision());

2
arch/arm/boards/embest-riotboard/board.c
View File

@ -70,7 +70,7 @@ static int riotboard_device_init(void)
phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3.barebox",
BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0);
BBU_HANDLER_FLAG_DEFAULT);
return 0;
}

35
arch/arm/boards/freescale-mx51-babbage/board.c
View File

@ -14,6 +14,8 @@
*
*/
#define pr_fmt(fmt) "babbage: " fmt
#include <common.h>
#include <init.h>
#include <environment.h>
@ -44,17 +46,10 @@
#define MX51_CCM_CACRR 0x10
static void babbage_power_init(void)
static void babbage_power_init(struct mc13xxx *mc13xxx)
{
struct mc13xxx *mc13xxx;
u32 val;
mc13xxx = mc13xxx_get();
if (!mc13xxx) {
printf("could not get PMIC\n");
return;
}
/* Write needed to Power Gate 2 register */
mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val);
val &= ~0x10000;
@ -149,28 +144,26 @@ static void babbage_power_init(void)
mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
udelay(200);
}
extern char flash_header_imx51_babbage_start[];
extern char flash_header_imx51_babbage_end[];
static int imx51_babbage_late_init(void)
{
if (!of_machine_is_compatible("fsl,imx51-babbage"))
return 0;
babbage_power_init();
pr_info("initialized PMIC\n");
console_flush();
imx51_init_lowlevel(800);
clock_notifier_call_chain();
}
static int imx51_babbage_init(void)
{
if (!of_machine_is_compatible("fsl,imx51-babbage"))
return 0;
mc13xxx_register_init_callback(babbage_power_init);
armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0",
BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx51_babbage_start,
flash_header_imx51_babbage_end - flash_header_imx51_babbage_start, 0);
BBU_HANDLER_FLAG_DEFAULT);
return 0;
}
late_initcall(imx51_babbage_late_init);
coredevice_initcall(imx51_babbage_init);

6
arch/arm/boards/freescale-mx53-qsb/board.c
View File

@ -76,9 +76,6 @@ static void loco_fec_reset(void)
#define MX53_LOCO_USB_PWREN IMX_GPIO_NR(7, 8)
extern char flash_header_imx53_loco_start[];
extern char flash_header_imx53_loco_end[];
static int loco_late_init(void)
{
struct mc13xxx *mc34708;
@ -162,8 +159,7 @@ static int loco_late_init(void)
armlinux_set_architecture(MACH_TYPE_MX53_LOCO);
imx53_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0",
BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx53_loco_start,
flash_header_imx53_loco_end - flash_header_imx53_loco_start, 0);
BBU_HANDLER_FLAG_DEFAULT);
return 0;
}

7
arch/arm/boards/freescale-mx53-vmx53/board.c
View File

@ -25,9 +25,6 @@
#include <asm/armlinux.h>
#include <mach/bbu.h>
extern char flash_header_imx53_vmx53_start[];
extern char flash_header_imx53_vmx53_end[];
static int vmx53_late_init(void)
{
if (!of_machine_is_compatible("voipac,imx53-dmm-668"))
@ -39,9 +36,7 @@ static int vmx53_late_init(void)
barebox_set_hostname("vmx53");
imx53_bbu_internal_nand_register_handler("nand",
BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx53_vmx53_start,
flash_header_imx53_vmx53_end - flash_header_imx53_vmx53_start,
SZ_512K, 0);
BBU_HANDLER_FLAG_DEFAULT, SZ_512K);
return 0;
}

2
arch/arm/boards/freescale-mx6-sabrelite/board.c
View File

@ -165,7 +165,7 @@ static int sabrelite_devices_init(void)
armlinux_set_architecture(3769);
imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0);
BBU_HANDLER_FLAG_DEFAULT);
return 0;
}

6
arch/arm/boards/guf-santaro/board.c
View File

@ -60,10 +60,8 @@ static int santaro_device_init(void)
}
}
imx6_bbu_internal_mmc_register_handler("sd", "/dev/mmc1",
flag_sd, NULL, 0, 0);
imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3.boot0",
flag_emmc, NULL, 0, 0);
imx6_bbu_internal_mmc_register_handler("sd", "/dev/mmc1", flag_sd);
imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3.boot0", flag_emmc);
return 0;
}

5
arch/arm/boards/guf-vincell/board.c
View File

@ -259,9 +259,6 @@ static struct imx_nand_platform_data nand_info = {
.flash_bbt = 1,
};
static struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
};
static struct i2c_board_info i2c_devices[] = {
{
I2C_BOARD_INFO("da9053", 0x48),
@ -293,7 +290,7 @@ static int vincell_devices_init(void)
dev_add_bb_dev("env_raw", "env0");
imx53_bbu_internal_nand_register_handler("nand",
BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry), 3 * SZ_128K, 0xf8020000);
BBU_HANDLER_FLAG_DEFAULT, 3 * SZ_128K);
return 0;
}

14
arch/arm/boards/karo-tx53/board.c
View File

@ -198,14 +198,6 @@ static inline void tx53_fec_init(void)
ARRAY_SIZE(tx53_fec_pads));
}
#define DCD_NAME_1011 static struct imx_dcd_v2_entry dcd_entry_1011
#include "dcd-data-1011.h"
#define DCD_NAME_XX30 static u32 dcd_entry_xx30
#include "dcd-data-xx30.h"
static int tx53_devices_init(void)
{
imx53_iim_register_fec_ethaddr();
@ -218,12 +210,10 @@ static int tx53_devices_init(void)
/* rev xx30 can boot from nand or USB */
imx53_bbu_internal_nand_register_handler("nand-xx30",
BBU_HANDLER_FLAG_DEFAULT, (void *)dcd_entry_xx30,
sizeof(dcd_entry_xx30), SZ_512K, 0);
BBU_HANDLER_FLAG_DEFAULT, SZ_512K);
/* rev 1011 can boot from MMC/SD, other bootsource currently unknown */
imx53_bbu_internal_mmc_register_handler("mmc-1011", "/dev/disk0",
0, (void *)dcd_entry_1011, sizeof(dcd_entry_1011), 0);
imx53_bbu_internal_mmc_register_handler("mmc-1011", "/dev/disk0", 0);
return 0;
}

94
arch/arm/boards/karo-tx53/dcd-data-1011.h
View File

@ -1,94 +0,0 @@
DCD_NAME_1011[] = {
{ .addr = cpu_to_be32(0x53fd406c), .val = cpu_to_be32(0xffffffff), },
{ .addr = cpu_to_be32(0x53fd4070), .val = cpu_to_be32(0xffffffff), },
{ .addr = cpu_to_be32(0x53fd4074), .val = cpu_to_be32(0xffffffff), },
{ .addr = cpu_to_be32(0x53fd4078), .val = cpu_to_be32(0xffffffff), },
{ .addr = cpu_to_be32(0x53fd407c), .val = cpu_to_be32(0xffffffff), },
{ .addr = cpu_to_be32(0x53fd4080), .val = cpu_to_be32(0xffffffff), },
{ .addr = cpu_to_be32(0x53fd4088), .val = cpu_to_be32(0xffffffff), },
{ .addr = cpu_to_be32(0x53fa8174), .val = cpu_to_be32(0x00000011), },
{ .addr = cpu_to_be32(0x63fd800c), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00200000), },
{ .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00200000), },
{ .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00200000), },
{ .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00200000), },
{ .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00200040), },
{ .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00200040), },
{ .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00200040), },
{ .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00200040), },
{ .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00200040), },
{ .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00200040), },
{ .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00200000), },
{ .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00200000), },
{ .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00200000), },
{ .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00200000), },
{ .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00200000), },
{ .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00200000), },
{ .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00280000), },
{ .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00280000), },
{ .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00280000), },
{ .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00280000), },
{ .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000200), },
{ .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x06000000), },
{ .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x36353b38), },
{ .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x49434942), },
{ .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), },
{ .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01350138), },
{ .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x01380139), },
{ .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00001710), },
{ .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x84110000), },
{ .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x4d5122d2), },
{ .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb6f18a22), },
{ .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x00c700db), },
{ .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
{ .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f000e), },
{ .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12272000), },
{ .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x00030012), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008010), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0a528030), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x03868031), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00068031), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), },
{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00033332), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00448031), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008018), },
{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
{ .addr = cpu_to_be32(0x53fa8004), .val = cpu_to_be32(0x00194005), },
{ .addr = cpu_to_be32(0x53fa819c), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa81a0), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa81a4), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa81a8), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa81ac), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa81b0), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa81b4), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa81b8), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa81dc), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa81e0), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8228), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa822c), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8230), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8234), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa8238), .val = cpu_to_be32(0x00000000), },
{ .addr = cpu_to_be32(0x53fa84ec), .val = cpu_to_be32(0x000000e4), },
{ .addr = cpu_to_be32(0x53fa84f0), .val = cpu_to_be32(0x000000e4), },
{ .addr = cpu_to_be32(0x53fa84f4), .val = cpu_to_be32(0x000000e4), },
{ .addr = cpu_to_be32(0x53fa84f8), .val = cpu_to_be32(0x000000e4), },
{ .addr = cpu_to_be32(0x53fa84fc), .val = cpu_to_be32(0x000000e4), },
{ .addr = cpu_to_be32(0x53fa8500), .val = cpu_to_be32(0x000000e4), },
{ .addr = cpu_to_be32(0x53fa8504), .val = cpu_to_be32(0x000000e4), },
{ .addr = cpu_to_be32(0x53fa8508), .val = cpu_to_be32(0x000000e4), },
{ .addr = cpu_to_be32(0x53fa852c), .val = cpu_to_be32(0x00000004), },
{ .addr = cpu_to_be32(0x53fa8530), .val = cpu_to_be32(0x00000004), },
{ .addr = cpu_to_be32(0x53fa85a0), .val = cpu_to_be32(0x00000004), },
{ .addr = cpu_to_be32(0x53fa85a4), .val = cpu_to_be32(0x00000004), },
{ .addr = cpu_to_be32(0x53fa85a8), .val = cpu_to_be32(0x000000e4), },
{ .addr = cpu_to_be32(0x53fa85ac), .val = cpu_to_be32(0x000000e4), },
{ .addr = cpu_to_be32(0x53fa85b0), .val = cpu_to_be32(0x00000004), },
};

144
arch/arm/boards/karo-tx53/dcd-data-xx30.h
View File

@ -1,144 +0,0 @@
#define DCD_ITEM(adr, val) cpu_to_be32(adr), cpu_to_be32(val)
#define DCD_WR_CMD(len) cpu_to_be32(0xcc << 24 | (len) << 8 | 0x04)
#define DCD_CHECK_CMD(a, b, c) cpu_to_be32(a), cpu_to_be32(b), cpu_to_be32(c)
/*
* This board uses advanced features of the DCD which do not corporate
* well with our flash header defines. The DCD consists of commands which
* have the length econded into them. Normally the DCDs only have a single
* command (DCD_COMMAND_WRITE_TAG) which is already part of struct
* imx_flash_header_v2. Now this board uses multiple commands, so we cannot
* calculate the command length using sizeof(dcd_entry).
*/
DCD_NAME_XX30[] = {
DCD_ITEM(0x53fd4068, 0xffcc0fff),
DCD_ITEM(0x53fd406c, 0x000fffc3),
DCD_ITEM(0x53fd4070, 0x033c0000),
DCD_ITEM(0x53fd4074, 0x00000000),
DCD_ITEM(0x53fd4078, 0x00000000),
DCD_ITEM(0x53fd407c, 0x00fff033),
DCD_ITEM(0x53fd4080, 0x0f00030f),
DCD_ITEM(0x53fd4084, 0xfff00000),
DCD_ITEM(0x53fd4088, 0x00000000),
DCD_ITEM(0x53fa8174, 0x00000011),
DCD_ITEM(0x53fa8318, 0x00000011),
DCD_ITEM(0x63fd800c, 0x00000000),
DCD_ITEM(0x53fd4014, 0x00888944),
DCD_ITEM(0x53fd4018, 0x00016154),
DCD_ITEM(0x53fa8724, 0x04000000),
DCD_ITEM(0x53fa86f4, 0x00000000),
DCD_ITEM(0x53fa8714, 0x00000000),
DCD_ITEM(0x53fa86fc, 0x00000080),
DCD_ITEM(0x53fa8710, 0x00000000),
DCD_ITEM(0x53fa8708, 0x00000040),
DCD_ITEM(0x53fa8584, 0x00280000),
DCD_ITEM(0x53fa8594, 0x00280000),
DCD_ITEM(0x53fa8560, 0x00280000),
DCD_ITEM(0x53fa8554, 0x00280000),
DCD_ITEM(0x53fa857c, 0x00a80040),
DCD_ITEM(0x53fa8590, 0x00a80040),
DCD_ITEM(0x53fa8568, 0x00a80040),
DCD_ITEM(0x53fa8558, 0x00a80040),
DCD_ITEM(0x53fa8580, 0x00280040),
DCD_ITEM(0x53fa8578, 0x00280000),
DCD_ITEM(0x53fa8564, 0x00280040),
DCD_ITEM(0x53fa8570, 0x00280000),
DCD_ITEM(0x53fa858c, 0x000000c0),
DCD_ITEM(0x53fa855c, 0x000000c0),
DCD_ITEM(0x53fa8574, 0x00280000),
DCD_ITEM(0x53fa8588, 0x00280000),
DCD_ITEM(0x53fa86f0, 0x00280000),
DCD_ITEM(0x53fa8720, 0x00280000),
DCD_ITEM(0x53fa8718, 0x00280000),
DCD_ITEM(0x53fa871c, 0x00280000),
DCD_ITEM(0x53fa8728, 0x00280000),
DCD_ITEM(0x53fa872c, 0x00280000),
DCD_ITEM(0x63fd904c, 0x001f001f),
DCD_ITEM(0x63fd9050, 0x001f001f),
DCD_ITEM(0x63fd907c, 0x011e011e),
DCD_ITEM(0x63fd9080, 0x011f0120),
DCD_ITEM(0x63fd9088, 0x3a393d3b),
DCD_ITEM(0x63fd9090, 0x3f3f3f3f),
DCD_ITEM(0x63fd9018, 0x00011740),
DCD_ITEM(0x63fd9000, 0x83190000),
DCD_ITEM(0x63fd900c, 0x3f435316),
DCD_ITEM(0x63fd9010, 0xb66e0a63),
DCD_ITEM(0x63fd9014, 0x01ff00db),
DCD_ITEM(0x63fd902c, 0x000026d2),
DCD_ITEM(0x63fd9030, 0x00430f24),
DCD_ITEM(0x63fd9008, 0x1b221010),
DCD_ITEM(0x63fd9004, 0x00030012),
DCD_ITEM(0x63fd901c, 0x00008032),
DCD_ITEM(0x63fd901c, 0x00008033),
DCD_ITEM(0x63fd901c, 0x00408031),
DCD_ITEM(0x63fd901c, 0x055080b0),
DCD_ITEM(0x63fd9020, 0x00005800),
DCD_ITEM(0x63fd9058, 0x00011112),
DCD_ITEM(0x63fd90d0, 0x00000003),
DCD_ITEM(0x63fd901c, 0x04008010),
DCD_ITEM(0x63fd901c, 0x00008040),
DCD_ITEM(0x63fd9040, 0x0539002b),
DCD_CHECK_CMD(0xcf000c04, 0x63fd9040, 0x00010000),
DCD_WR_CMD(0x24),
DCD_ITEM(0x63fd901c, 0x00048033),
DCD_ITEM(0x63fd901c, 0x00848231),
DCD_ITEM(0x63fd901c, 0x00000000),
DCD_ITEM(0x63fd9048, 0x00000001),
DCD_CHECK_CMD(0xcf000c04, 0x63fd9048, 0x00000001),
DCD_WR_CMD(0x2c),
DCD_ITEM(0x63fd901c, 0x00048031),
DCD_ITEM(0x63fd901c, 0x00008033),
DCD_ITEM(0x63fd901c, 0x04008010),
DCD_ITEM(0x63fd901c, 0x00048033),
DCD_ITEM(0x63fd907c, 0x90000000),
DCD_CHECK_CMD(0xcf000c04, 0x63fd907c, 0x90000000),
DCD_WR_CMD(0x2c),
DCD_ITEM(0x63fd901c, 0x00008033),
DCD_ITEM(0x63fd901c, 0x00000000),
DCD_ITEM(0x63fd901c, 0x04008010),
DCD_ITEM(0x63fd901c, 0x00048033),
DCD_ITEM(0x63fd90a4, 0x00000010),
DCD_CHECK_CMD(0xcf000c04, 0x63fd90a4, 0x00000010),
DCD_WR_CMD(0x24),
DCD_ITEM(0x63fd901c, 0x00008033),
DCD_ITEM(0x63fd901c, 0x04008010),
DCD_ITEM(0x63fd901c, 0x00048033),
DCD_ITEM(0x63fd90a0, 0x00000010),
DCD_CHECK_CMD(0xcf000c04, 0x63fd90a0, 0x00000010),
DCD_WR_CMD(0x010c),
DCD_ITEM(0x63fd901c, 0x00008033),
DCD_ITEM(0x63fd901c, 0x00000000),
DCD_ITEM(0x53fa8004, 0x00194005),
DCD_ITEM(0x53fa819c, 0x00000000),
DCD_ITEM(0x53fa81a0, 0x00000000),
DCD_ITEM(0x53fa81a4, 0x00000000),
DCD_ITEM(0x53fa81a8, 0x00000000),
DCD_ITEM(0x53fa81ac, 0x00000000),
DCD_ITEM(0x53fa81b0, 0x00000000),
DCD_ITEM(0x53fa81b4, 0x00000000),
DCD_ITEM(0x53fa81b8, 0x00000000),
DCD_ITEM(0x53fa81dc, 0x00000000),
DCD_ITEM(0x53fa81e0, 0x00000000),
DCD_ITEM(0x53fa8228, 0x00000000),
DCD_ITEM(0x53fa822c, 0x00000000),
DCD_ITEM(0x53fa8230, 0x00000000),
DCD_ITEM(0x53fa8234, 0x00000000),
DCD_ITEM(0x53fa8238, 0x00000000),
DCD_ITEM(0x53fa84ec, 0x000000e4),
DCD_ITEM(0x53fa84f0, 0x000000e4),
DCD_ITEM(0x53fa84f4, 0x000000e4),
DCD_ITEM(0x53fa84f8, 0x000000e4),
DCD_ITEM(0x53fa84fc, 0x000000e4),
DCD_ITEM(0x53fa8500, 0x000000e4),
DCD_ITEM(0x53fa8504, 0x000000e4),
DCD_ITEM(0x53fa8508, 0x000000e4),
DCD_ITEM(0x53fa852c, 0x00000004),
DCD_ITEM(0x53fa8530, 0x00000004),
DCD_ITEM(0x53fa85a0, 0x00000004),
DCD_ITEM(0x53fa85a4, 0x00000004),
DCD_ITEM(0x53fa85a8, 0x000000e4),
DCD_ITEM(0x53fa85ac, 0x000000e4),
DCD_ITEM(0x53fa85b0, 0x00000004),
};

22
arch/arm/boards/phytec-phycard-imx27/lowlevel.c
View File

@ -8,6 +8,7 @@
#include <init.h>
#include <io.h>
#include <config.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
#include <mach/imx27-regs.h>
#include <mach/imx-pll.h>
@ -57,14 +58,12 @@ static void sdram_init(void)
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
}
void __bare_init __naked barebox_arm_reset_vector(void)
void __bare_init __naked phytec_phycard_imx27_common_init(void *fdt)
{
unsigned long r;
arm_cpu_lowlevel_init();
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
@ -74,7 +73,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0xa0000000 && r < 0xc0000000)
imx27_barebox_entry(NULL);
imx27_barebox_entry(fdt);
/* 399 MHz */
writel(IMX_PLL_PD(0) |
@ -99,5 +98,18 @@ void __bare_init __naked barebox_arm_reset_vector(void)
sdram_init();
imx27_barebox_boot_nand_external(0);
imx27_barebox_boot_nand_external(fdt);
}
extern char __dtb_imx27_phytec_phycard_s_rdk_bb_start[];
ENTRY_FUNCTION(start_phytec_phycard_imx27, r0, r1, r2)
{
void *fdt;
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
fdt = __dtb_imx27_phytec_phycard_s_rdk_bb_start - get_runtime_offset();
phytec_phycard_imx27_common_init(fdt);
}

13
arch/arm/boards/solidrun-hummingboard/board.c
View File

@ -20,6 +20,7 @@
#include <envfs.h>
#include <gpio.h>
#include <init.h>
#include <mach/bbu.h>
#include <mach/generic.h>
#include <mach/imx6-regs.h>
#include <mach/imx6.h>
@ -75,6 +76,18 @@ static int hummingboard_device_init(void)
}
device_initcall(hummingboard_device_init);
static int hummingboard_late_init(void)
{
if (!of_machine_is_compatible("solidrun,hummingboard"))
return 0;
imx6_bbu_internal_mmc_register_handler("sdcard", "/dev/mmc1.barebox",
BBU_HANDLER_FLAG_DEFAULT);
return 0;
}
late_initcall(hummingboard_late_init);
static int hummingboard_lwl_init(void)
{
if (!of_machine_is_compatible("solidrun,hummingboard"))

15
arch/arm/boards/tqma53/board.c
View File

@ -20,20 +20,29 @@
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <mach/bbu.h>
static int tqma53_devices_init(void)
{
char *of_env_path = "/chosen/environment-emmc";
char *of_env_path;
unsigned bbu_flag_emmc = 0, bbu_flag_sd = 0;
if (!of_machine_is_compatible("tq,tqma53"))
return 0;
barebox_set_model("TQ tqma53");
barebox_set_hostname("tqma53");
if (bootsource_get() == BOOTSOURCE_MMC &&
bootsource_get_instance() == 1)
bootsource_get_instance() == 1) {
of_env_path = "/chosen/environment-sd";
bbu_flag_sd = BBU_HANDLER_FLAG_DEFAULT;
} else {
of_env_path = "/chosen/environment-emmc";
bbu_flag_emmc = BBU_HANDLER_FLAG_DEFAULT;
}
imx53_bbu_internal_mmc_register_handler("sd", "/dev/mmc1", bbu_flag_sd);
imx53_bbu_internal_mmc_register_handler("emmc", "/dev/mmc2", bbu_flag_emmc);
of_device_enable_path(of_env_path);

24
arch/arm/boards/tqma6x/board.c
View File

@ -98,34 +98,16 @@ static int tqma6x_enet_init(void)
}
fs_initcall(tqma6x_enet_init);
extern char flash_header_tqma6dl_start[];
extern char flash_header_tqma6dl_end[];
extern char flash_header_tqma6q_start[];
extern char flash_header_tqma6q_end[];
static int tqma6x_env_init(void)
{
void *flash_header_start;
void *flash_header_end;
if (of_machine_is_compatible("tq,tqma6s")) {
flash_header_start = (void *)flash_header_tqma6dl_start;
flash_header_end = (void *)flash_header_tqma6dl_end;
} else if (of_machine_is_compatible("tq,tqma6q")) {
flash_header_start = (void *)flash_header_tqma6q_start;
flash_header_end = (void *)flash_header_tqma6q_end;
} else {
if (!of_machine_is_compatible("tq,mba6x"))
return 0;
}
devfs_add_partition("m25p0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "m25p0.barebox");
imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_start,
flash_header_end - flash_header_start, 0);
imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc2.boot0",
0, (void *)flash_header_start, flash_header_end - flash_header_start, 0);
BBU_HANDLER_FLAG_DEFAULT);
imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc2.boot0", 0);
device_detect_by_name("mmc2");

38
arch/arm/configs/phytec-phycard-imx27_defconfig → arch/arm/configs/imx_defconfig
View File

@ -1,16 +1,19 @@
CONFIG_BUILTIN_DTB=y
CONFIG_BUILTIN_DTB_NAME="imx27-phytec-phycard-s-rdk"
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_TX25=y
CONFIG_MACH_PCA100=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x01000000
CONFIG_TEXT_BASE=0x0
CONFIG_MALLOC_SIZE=0x0
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_RELOCATABLE=y
CONFIG_PANIC_HANG=y
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
@ -19,25 +22,32 @@ CONFIG_MENU=y
CONFIG_BLSPEC=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH=""
CONFIG_RESET_SOURCE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_READF=y
CONFIG_CMD_LET=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENUTREE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_LN=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_MM=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_UBIFORMAT=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
@ -68,8 +78,13 @@ CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
# CONFIG_SPI is not set
CONFIG_DRIVER_SPI_IMX=y
CONFIG_I2C=y
CONFIG_I2C_IMX=y
CONFIG_MTD=y
CONFIG_MTD_RAW_DEVICE=y
CONFIG_DRIVER_CFI=y
CONFIG_CFI_BUFFER_WRITE=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_SOFT is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
@ -81,9 +96,18 @@ CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
CONFIG_MCI=y
CONFIG_MCI_IMX=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_GPIO_OF=y
CONFIG_LED_TRIGGERS=y
CONFIG_EEPROM_AT25=y
CONFIG_EEPROM_AT24=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
CONFIG_IMX_WEIM=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y

87
arch/arm/configs/tx25stk5_defconfig
View File

@ -1,87 +0,0 @@
CONFIG_ARCH_IMX=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_TX25=y
CONFIG_IMX_IIM=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x91d00000
CONFIG_MALLOC_SIZE=0x1000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/karo-tx25/env"
CONFIG_RESET_SOURCE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_LN=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DETECT=y
CONFIG_CMD_WD=y
CONFIG_NET=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_OFDEVICE=y
CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_IMX=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX=y
CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y
CONFIG_MCI=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_ZLIB=y
CONFIG_LZO_DECOMPRESS=y

1
arch/arm/dts/Makefile
View File

@ -55,6 +55,7 @@ pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab
pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
pbl-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
pbl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o

2
arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts
View File

@ -2,7 +2,7 @@
* Barebox specific DT overlay for Phytec PCA100 RDK
*/
#include "imx27-phytec-phycard-s-rdk.dts"
#include <arm/imx27-phytec-phycard-s-rdk.dts>
/ {
chosen {

164
arch/arm/dts/imx27-phytec-phycard-s-rdk.dts
View File

@ -1,164 +0,0 @@
/*
* Copyright 2012 Markus Pargmann, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx27-phytec-phycard-s-som.dtsi"
/ {
model = "Phytec pca100 rapid development kit";
compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
display: display {
model = "Primeview-PD050VL1";
native-mode = <&timing0>;
bits-per-pixel = <16>; /* non-standard but required */
fsl,pcr = <0xf0c88080>; /* non-standard but required */
display-timings {
timing0: 640x480 {
hactive = <640>;
vactive = <480>;
hback-porch = <112>;
hfront-porch = <36>;
hsync-len = <32>;
vback-porch = <33>;
vfront-porch = <33>;
vsync-len = <2>;
clock-frequency = <25000000>;
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3v3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&fb {
display = <&display>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
adc@64 {
compatible = "maxim,max1037";
vcc-supply = <&reg_3v3>;
reg = <0x64>;
};
};
&iomuxc {
imx27-phycard-s-rdk {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_owire1: owire1grp {
fsl,pins = <
MX27_PAD_RTCK__OWIRE 0x0
>;
};
pinctrl_sdhc2: sdhc2grp {
fsl,pins = <
MX27_PAD_SD2_CLK__SD2_CLK 0x0
MX27_PAD_SD2_CMD__SD2_CMD 0x0
MX27_PAD_SD2_D0__SD2_D0 0x0
MX27_PAD_SD2_D1__SD2_D1 0x0
MX27_PAD_SD2_D2__SD2_D2 0x0
MX27_PAD_SD2_D3__SD2_D3 0x0
MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX27_PAD_UART2_TXD__UART2_TXD 0x0
MX27_PAD_UART2_RXD__UART2_RXD 0x0
MX27_PAD_UART2_CTS__UART2_CTS 0x0
MX27_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX27_PAD_UART3_TXD__UART3_TXD 0x0
MX27_PAD_UART3_RXD__UART3_RXD 0x0
MX27_PAD_UART3_CTS__UART3_CTS 0x0
MX27_PAD_UART3_RTS__UART3_RTS 0x0
>;
};
};
};
&owire {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_owire1>;
status = "okay";
};
&sdhci2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhc2>;
cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart1 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
fsl,uart-has-rtscts;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};

103
arch/arm/dts/imx27-phytec-phycard-s-som.dtsi
View File

@ -1,103 +0,0 @@
/*
* Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
* and Markus Pargmann, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx27.dtsi"
/ {
model = "Phytec pca100";
compatible = "phytec,imx27-pca100", "fsl,imx27";
memory {
reg = <0xa0000000 0x08000000>; /* 128MB */
};
};
&cspi1 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
<&gpio4 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
at24@52 {
compatible = "at,24c32";
pagesize = <32>;
reg = <0x52>;
};
};
&iomuxc {
imx27-phycard-s-som {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX27_PAD_SD3_CMD__FEC_TXD0 0x0
MX27_PAD_SD3_CLK__FEC_TXD1 0x0
MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
MX27_PAD_ATA_DATA7__FEC_MDC 0x0
MX27_PAD_ATA_DATA8__FEC_CRS 0x0
MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
MX27_PAD_ATA_DATA13__FEC_COL 0x0
MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
>;
};
pinctrl_nfc: nfcgrp {
fsl,pins = <
MX27_PAD_NFRB__NFRB 0x0
MX27_PAD_NFCLE__NFCLE 0x0
MX27_PAD_NFWP_B__NFWP_B 0x0
MX27_PAD_NFCE_B__NFCE_B 0x0
MX27_PAD_NFALE__NFALE 0x0
MX27_PAD_NFRE_B__NFRE_B 0x0
MX27_PAD_NFWE_B__NFWE_B 0x0
>;
};
};
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
};

38
arch/arm/dts/imx51-babbage.dts
View File

@ -14,7 +14,7 @@
/ {
chosen {
linux,stdout-path = "/soc/aips@70000000/serial@73fbc000";
stdout-path = &uart1;
environment@0 {
compatible = "barebox,environment";
@ -36,3 +36,39 @@
&iim {
barebox,provide-mac-address = <&fec 1 9>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx51-babbage {
pinctrl_fec: fecgrp {
/*
* Overwrite upstream FEC iomux settings since these currently
* have NO_PAD_CTRL instead of real settings. Remove this once
* this is fixed upstream.
*/
fsl,pins = <
MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
>;
};
};
};

2
arch/arm/dts/imx51-genesi-efika-sb.dts
View File

@ -19,7 +19,7 @@
compatible = "genesi,imx51-sb", "fsl,imx51";
chosen {
linux,stdout-path = "/soc/aips@70000000/serial@73fbc000";
stdout-path = &uart1;
environment-sd {
compatible = "barebox,environment";

8
arch/arm/dts/imx53-mba53.dts
View File

@ -33,3 +33,11 @@
reg = <0x80000 0x80000>;
};
};
&usbh1 {
phy_type = "utmi";
};
&usbotg {
phy_type = "utmi";
};

2
arch/arm/dts/imx53-qsb-common.dtsi
View File

@ -12,7 +12,7 @@
/ {
chosen {
linux,stdout-path = "/soc/aips@50000000/serial@53fbc000";
stdout-path = &uart1;
environment@0 {
compatible = "barebox,environment";

1
arch/arm/dts/imx53-qsb.dts
View File

@ -11,4 +11,5 @@
*/
#include <arm/imx53-qsb.dts>
#include "imx53.dtsi"
#include "imx53-qsb-common.dtsi"

1
arch/arm/dts/imx53-qsrb.dts
View File

@ -11,4 +11,5 @@
*/
#include <arm/imx53-qsrb.dts>
#include "imx53.dtsi"
#include "imx53-qsb-common.dtsi"

1
arch/arm/dts/imx53-voipac-bsb.dts
View File

@ -10,3 +10,4 @@
*/
#include <arm/imx53-voipac-bsb.dts>
#include "imx53.dtsi"

8
arch/arm/dts/imx53.dtsi
View File

@ -1 +1,7 @@
#include <arm/imx53.dtsi>
/ {
aliases {
pwm0 = &pwm1;
pwm1 = &pwm2;
ipu0 = &ipu;
};
};

79
arch/arm/dts/imx6dl-hummingboard.dts
View File

@ -11,9 +11,6 @@
#include "imx6qdl-microsom-ar8035.dtsi"
/ {
model = "SolidRun HummingBoard DL/Solo";
compatible = "solidrun,hummingboard", "fsl,imx6dl";
chosen {
linux,stdout-path = &uart1;
@ -26,85 +23,9 @@
memory {
reg = <0x10000000 0x20000000>;
};
ir_recv: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 2 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
};
codec: spdif-transmitter {
compatible = "linux,spdif-dit";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_spdif>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
/* IMX6 doesn't implement this yet */
spdif-controller = <&spdif>;
spdif-out;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
/*
* Not fitted on Carrier-1 board... yet
status = "okay";
rtc: pcf8523@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
*/
};
&iomuxc {
hummingboard {
pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
>;
};
pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
fsl,pins = <MX6QDL_I2C1_PINGRP1>;
};
pinctrl_hummingboard_spdif: hummingboard-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
};
pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1f071
>;
};
};
};
&spdif {
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usdhc2>;
vmmc-supply = <&reg_3p3v>;
fsl,cd-controller;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;

143
arch/arm/dts/imx6q-gk802.dts
View File

@ -6,158 +6,17 @@
* kind, whether express or implied.
*/
/dts-v1/;
#include <arm/imx6q-gk802.dts>
#include "imx6q.dtsi"
/ {
model = "Zealz GK802";
compatible = "zealz,imx6q-gk802", "fsl,imx6q";
chosen {
linux,stdout-path = "/soc/aips-bus@02100000/serial@021f0000";
};
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
gpio-keys {
compatible = "gpio-keys";
recovery-button {
label = "recovery";
gpios = <&gpio3 16 1>;
linux,code = <0x198>; /* KEY_RESTART */
gpio-key,wakeup;
};
};
};
/* Internal I2C */
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_gk802>;
clock-frequency = <100000>;
status = "okay";
/* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */
eeprom: dm2016@51 {
compatible = "sdmc,dm2016";
reg = <0x51>;
};
};
/* External I2C via HDMI */
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_gk802>;
clock-frequency = <100000>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
/* Recovery button, active-low */
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x100b1
/* RTL8192CU enable GPIO, active-low */
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
>;
};
};
i2c2 {
pinctrl_i2c2_gk802: i2c2grp-1 {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
};
i2c3 {
pinctrl_i2c3_gk802: i2c3grp-1 {
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
>;
};
};
uart {
pinctrl_uart4: uart4grp {
fsl,pins = <MX6QDL_UART4_PINGRP1>;
};
};
usdhc {
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <MX6QDL_USDHC4_PINGRP_D4>;
};
};
};
&uart2 {
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
/* External USB-A port (USBOTG) */
&usbotg {
phy_type = "utmi";
dr_mode = "host";
disable-over-current;
status = "okay";
};
/* Internal USB port (USBH1), connected to RTL8192CU */
&usbh1 {
phy_type = "utmi";
dr_mode = "host";
disable-over-current;
status = "okay";
};
/* External microSD */
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <4>;
cd-gpios = <&gpio6 11 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
/* Internal microSD */
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};

49
arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi
View File

@ -47,7 +47,15 @@
imx6q-phytec-pcaaxl3 {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_ENET_PINGRP4
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1b0b0
MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1b0b0
@ -61,21 +69,50 @@
};
pinctrl_gpmi_nand: gpmigrp {
fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1>;
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP1>;
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <MX6QDL_UART3_PINGRP3>;
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_USDHC3_PINGRP_D4
MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000 /* CD */
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000 /* CD */
>;
};
};

28
arch/arm/dts/imx6q-var-custom.dts
View File

@ -42,26 +42,42 @@
imx6q-variscite-custom {
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP1>;
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <MX6QDL_I2C3_PINGRP3>;
fsl,pins = <
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc2_cd: usdhc2cd {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_UART1_PINGRP1>;
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
};
};

43
arch/arm/dts/imx6q-var-som.dtsi
View File

@ -83,17 +83,52 @@
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0)
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* KSZ9031 PHY Reset */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* KSZ9031 PHY Reset */
>;
};
pinctrl_gpmi_nand: gpmigrp {
fsl,pins = <MX6QDL_GPMI_NAND_PINGRP1>;
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <MX6QDL_I2C2_PINGRP2>;
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
};
};

142
arch/arm/dts/imx6qdl-dfi-fs700-m60.dtsi
View File

@ -1,22 +1,6 @@
#include <arm/imx6qdl-dfi-fs700-m60.dtsi>
/ {
regulators {
compatible = "simple-bus";
dummy_reg: fixed@0 {
compatible = "regulator-fixed";
regulator-name = "dummy-supply";
};
reg_usb_otg_vbus: usb_otg_vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
chosen {
linux,stdout-path = &uart1;
@ -27,138 +11,16 @@
};
};
&ecspi3 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf040b", "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
status = "okay";
phy-mode = "rgmii";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-dfi-fs700-m60 {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC irq */
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 /* MAX11801 irq */
MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* SD2 card detect */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_ENET_PINGRP1>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <MX6QDL_I2C2_PINGRP1>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_UART1_PINGRP1>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <MX6QDL_USBOTG_PINGRP2>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX6QDL_USDHC2_PINGRP_D4>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <MX6QDL_USDHC4_PINGRP_D8>;
};
};
ecspi3 {
pinctrl_ecspi3: ecspi3_csgrp {
fsl,pins = <
MX6QDL_ECSPI3_PINGRP1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
>;
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic: pf0100@08 {
compatible = "pf0100-regulator";
reg = <0x08>;
interrupt-parent = <&gpio7>;
interrupts = <13 8>;
};
};
&ocotp {
barebox,provide-mac-address = <&fec 0x620>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbh1 {
phy_type = "utmi";
dr_mode = "host";
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
phy_type = "utmi";
dr_mode = "host";
status = "okay";
};
&usdhc2 { /* module slot */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio2 2 0>;
status = "okay";
};
&usdhc3 { /* baseboard slot */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
};
&usdhc4 { /* eMMC */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
bus-width = <8>;
non-removable;
status = "okay";
};

9
arch/arm/dts/imx6qdl-mba6x.dtsi
View File

@ -119,11 +119,16 @@
&iomuxc {
imx6qdl-mba6x {
pinctrl_usbotg: usbotggrp {
fsl,pins = <MX6QDL_USBOTG_PINGRP1>;
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
fsl,pins = <
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
};
};

79
arch/arm/dts/imx6qdl-microsom.dtsi
View File

@ -4,90 +4,13 @@
* The code contained herein is licensed under the GNU General Public
* License version 2.
*/
/ {
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 0 0>;
enable-active-high;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_flexcan1>;
status = "okay";
};
&iomuxc {
microsom {
pinctrl_microsom_flexcan1: microsom-flexcan1 {
fsl,pins = <
MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
>;
};
pinctrl_microsom_uart1: microsom-uart1 {
fsl,pins = <MX6QDL_UART1_PINGRP1>;
};
pinctrl_microsom_usbotg: microsom-usbotg {
/*
* Similar to pinctrl_usbotg_2, but we want it
* pulled down for a fixed host connection.
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_uart1>;
status = "okay";
};
#include <arm/imx6qdl-microsom.dtsi>
&usbotg {
phy_type = "utmi";
dr_mode = "host";
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_usbotg>;
status = "okay";
};
&usbh1 {
phy_type = "utmi";
dr_mode = "host";
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};

378
arch/arm/dts/imx6qdl-nitrogen6x.dtsi
View File

@ -10,6 +10,7 @@
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <arm/imx6qdl-nitrogen6x.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@ -22,317 +23,20 @@
device-path = &flash, "partname:barebox-environment";
};
};
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_2p5v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
menu {
label = "Menu";
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
home {
label = "Home";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
back {
label = "Back";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
sound {
compatible = "fsl,imx6q-nitrogen6x-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-nitrogen6x-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <3>;
};
backlight_lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
backlight_lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&flash {
#address-cells = <1>;
#size-cells = <1>;
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b", "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox";
reg = <0x0 0x80000>;
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
partition@0 {
label = "barebox";
reg = <0x0 0x80000>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 27 0>;
txen-skew-ps = <0>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 201>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6q-nitrogen6x {
pinctrl_hog: hoggrp {
fsl,pins = <
/* SGTL5000 sys_mclk */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_ECSPI1_PINGRP1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0)
/* Phy reset */
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
/* Menu Button */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
/* Home Button */
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
/* Back Button */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
/* Volume Up Button */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
/* Volume Down Button */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP1>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_UART1_PINGRP2>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <MX6QDL_UART2_PINGRP1>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
/* power enable, high active */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_USDHC3_PINGRP_D4
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_USDHC4_PINGRP_D4
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
>;
};
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
};
@ -340,73 +44,11 @@
barebox,provide-mac-address = <&fec 0x620>;
};
&pcie {
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
phy_type = "utmi";
dr_mode = "host";
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
phy_type = "utmi";
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio2 6 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};

532
arch/arm/dts/imx6qdl-pingrp.h
View File

@ -1,532 +0,0 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX6QDL_PINGRP_H
#define __DTS_IMX6QDL_PINGRP_H
#define MX6QDL_AUDMUX_PINGRP1 \
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 \
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 \
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 \
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
#define MX6QDL_AUDMUX_PINGRP2 \
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 \
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 \
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 \
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
#define MX6QDL_AUDMUX_PINGRP3 \
MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 \
MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 \
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 \
#define MX6QDL_AUDMUX_PINGRP4 \
MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 \
MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 \
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
#define MX6QDL_AUDMUX_PINGRP5 \
MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 \
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 \
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 \
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
#define MX6QDL_ECSPI1_PINGRP1 \
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 \
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 \
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
#define MX6QDL_ECSPI1_PINGRP2 \
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 \
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 \
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
#define MX6QDL_ECSPI3_PINGRP1 \
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 \
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 \
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
#define MX6QDL_ENET_PINGRP_RGMII(rx_pad, tx_pad) \
MX6QDL_PAD_RGMII_RXC__RGMII_RXC rx_pad \
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 rx_pad \
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 rx_pad \
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 rx_pad \
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 rx_pad \
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL rx_pad \
MX6QDL_PAD_RGMII_TXC__RGMII_TXC tx_pad \
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 tx_pad \
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 tx_pad \
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 tx_pad \
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 tx_pad \
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL tx_pad \
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK tx_pad
#define MX6QDL_ENET_PINGRP_RGMII_MD(rx_pad, tx_pad) \
MX6QDL_ENET_PINGRP_RGMII(rx_pad, tx_pad) \
MX6QDL_PAD_ENET_MDIO__ENET_MDIO tx_pad \
MX6QDL_PAD_ENET_MDC__ENET_MDC tx_pad
#define MX6QDL_ENET_PINGRP1 \
MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0) \
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
#define MX6QDL_ENET_PINGRP2 \
MX6QDL_ENET_PINGRP_RGMII(0x1b0b0, 0x1b0b0) \
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 \
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
#define MX6QDL_ENET_PINGRP3 \
MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0) \
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
#define MX6QDL_ENET_PINGRP4 \
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 \
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 \
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 \
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 \
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 \
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 \
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 \
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 \
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
#define MX6QDL_ENET_PINGRP1_GPIO6 MX6QDL_ENET_PINGRP1 \
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
#define MX6QDL_ENET_PINGRP2_GPIO6 MX6QDL_ENET_PINGRP2 \
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
#define MX6QDL_ENET_PINGRP3_GPIO6 MX6QDL_ENET_PINGRP3 \
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
#define MX6QDL_ESAI_PINGRP1 \
MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030 \
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 \
MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 \
MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 \
MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030 \
MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 \
MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 \
MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030 \
MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
#define MX6QDL_ESAI_PINGRP2 \
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030 \
MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030 \
MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030 \
MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030 \
MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030 \
MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030 \
MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030 \
MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030 \
MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030 \
MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
#define MX6QDL_FLEXCAN1_PINGRP1 \
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 \
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
#define MX6QDL_FLEXCAN1_PINGRP2 \
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 \
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
#define MX6QDL_FLEXCAN2_PINGRP1 \
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 \
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
#define MX6QDL_GPMI_NAND_PINGRP1 \
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 \
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 \
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 \
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 \
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 \
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 \
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 \
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 \
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 \
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 \
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 \
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 \
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 \
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 \
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 \
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 \
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
#define MX6QDL_GPMI_NAND_PINGRP1_NODQS \
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 \
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 \
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 \
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 \
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 \
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 \
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 \
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 \
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 \
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 \
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 \
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 \
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 \
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 \
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 \
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
#define MX6QDL_HDMI_HDCP_PINGRP1 \
MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 \
MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
#define MX6QDL_HDMI_HDCP_PINGRP2 \
MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 \
MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
#define MX6QDL_HDMI_HDCP_PINGRP3 \
MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 \
MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
#define MX6QDL_HDMI_CEC_PINGRP1 \
MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
#define MX6QDL_HDMI_CEC_PINGRP2 \
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
#define MX6QDL_I2C1_PINGRP1 \
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 \
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
#define MX6QDL_I2C1_PINGRP2 \
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 \
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
#define MX6QDL_I2C2_PINGRP1 \
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 \
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
#define MX6QDL_I2C2_PINGRP2 \
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 \
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
#define MX6QDL_I2C2_PINGRP3 \
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 \
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
#define MX6QDL_I2C3_PINGRP1 \
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 \
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
#define MX6QDL_I2C3_PINGRP2 \
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 \
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
#define MX6QDL_I2C3_PINGRP3 \
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 \
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
#define MX6QDL_I2C3_PINGRP4 \
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 \
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
#define MX6QDL_IPU1_PINGRP1 \
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 \
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 \
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 \
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 \
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 \
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 \
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 \
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 \
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 \
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 \
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 \
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 \
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 \
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 \
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 \
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 \
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 \
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 \
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 \
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 \
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 \
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 \
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 \
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 \
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 \
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 \
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 \
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 \
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
/* parallel camera */
#define MX6QDL_IPU1_PINGRP2 \
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 \
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 \
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 \
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 \
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 \
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 \
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 \
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 \
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 \
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 \
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 \
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
/* parallel port 16-bit */
#define MX6QDL_IPU1_PINGRP3 \
MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 \
MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 \
MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 \
MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 \
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 \
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 \
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 \
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 \
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 \
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 \
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 \
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 \
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 \
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 \
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 \
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 \
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 \
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 \
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
#define MX6QDL_MLB_PINGRP1 \
MX6QDL_PAD_GPIO_3__MLB_CLK 0x71 \
MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 \
MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
#define MX6QDL_MLB_PINGRP2 \
MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71 \
MX6QDL_PAD_GPIO_6__MLB_SIG 0x71 \
MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
#define MX6QDL_PWM1_PINGRP1 \
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
#define MX6QDL_PWM3_PINGRP1 \
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
#define MX6QDL_SPDIF_PINGRP1 \
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
#define MX6QDL_SPDIF_PINGRP2 \
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 \
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
#define MX6QDL_SPDIF_PINGRP3 \
MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
#define MX6QDL_UART1_PINGRP1 \
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 \
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
#define MX6QDL_UART1_PINGRP2 \
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 \
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
#define MX6QDL_UART2_PINGRP1 \
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
/* DTE mode */
#define MX6QDL_UART2_PINGRP2 \
MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 \
MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
#define MX6QDL_UART2_PINGRP3 \
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 \
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
#define MX6QDL_UART3_PINGRP1 \
MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 \
MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 \
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
#define MX6QDL_UART3_PINGRP2 \
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 \
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
#define MX6QDL_UART3_PINGRP3 \
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 \
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
#define MX6QDL_UART4_PINGRP1 \
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 \
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
#define MX6QDL_UART5_PINGRP1 \
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 \
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
#define MX6QDL_USBOTG_PINGRP1 \
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
#define MX6QDL_USBOTG_PINGRP2 \
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
#define MX6QDL_USBH2_PINGRP1 \
MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 \
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
#define MX6QDL_USBH2_PINGRP2 \
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
#define MX6QDL_USBH3_PINGRP1 \
MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 \
MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
#define MX6QDL_USBH3_PINGRP2 \
MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
#define MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD1_CMD__SD1_CMD pad \
MX6QDL_PAD_SD1_CLK__SD1_CLK pad_clk \
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 pad \
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 pad \
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 pad \
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 pad_data3
#define MX6QDL_USDHC1_D8(pad, pad_data3, pad_clk) \
MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_NANDF_D0__SD1_DATA4 pad \
MX6QDL_PAD_NANDF_D1__SD1_DATA5 pad \
MX6QDL_PAD_NANDF_D2__SD1_DATA6 pad \
MX6QDL_PAD_NANDF_D3__SD1_DATA7 pad
#define MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD2_CMD__SD2_CMD pad \
MX6QDL_PAD_SD2_CLK__SD2_CLK pad_clk \
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 pad \
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 pad \
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 pad \
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 pad_data3
#define MX6QDL_USDHC2_D8(pad, pad_data3, pad_clk) \
MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_NANDF_D4__SD2_DATA4 pad \
MX6QDL_PAD_NANDF_D5__SD2_DATA5 pad \
MX6QDL_PAD_NANDF_D6__SD2_DATA6 pad \
MX6QDL_PAD_NANDF_D7__SD2_DATA7 pad
#define MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD3_CMD__SD3_CMD pad \
MX6QDL_PAD_SD3_CLK__SD3_CLK pad_clk \
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 pad \
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 pad \
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 pad \
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 pad_data3
#define MX6QDL_USDHC3_D8(pad, pad_data3, pad_clk) \
MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 pad \
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 pad \
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 pad \
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 pad
#define MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD4_CMD__SD4_CMD pad \
MX6QDL_PAD_SD4_CLK__SD4_CLK pad_clk \
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 pad \
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 pad \
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 pad \
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 pad_data3
#define MX6QDL_USDHC4_D8(pad, pad_data3, pad_clk) \
MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 pad \
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 pad \
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 pad \
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 pad
#define MX6QDL_USDHC1_PINGRP_D4 MX6QDL_USDHC1_D4(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC1_PINGRP_D4_100MHZ MX6QDL_USDHC1_D4(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC1_PINGRP_D4_200MHZ MX6QDL_USDHC1_D4(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC1_PINGRP_D8 MX6QDL_USDHC1_D8(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC1_PINGRP_D8_100MHZ MX6QDL_USDHC1_D8(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC1_PINGRP_D8_200MHZ MX6QDL_USDHC1_D8(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC2_PINGRP_D4 MX6QDL_USDHC2_D4(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC2_PINGRP_D4_100MHZ MX6QDL_USDHC2_D4(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC2_PINGRP_D4_200MHZ MX6QDL_USDHC2_D4(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC2_PINGRP_D8 MX6QDL_USDHC2_D8(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC2_PINGRP_D8_100MHZ MX6QDL_USDHC2_D8(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC2_PINGRP_D8_200MHZ MX6QDL_USDHC2_D8(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC3_PINGRP_D4 MX6QDL_USDHC3_D4(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC3_PINGRP_D4_100MHZ MX6QDL_USDHC3_D4(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC3_PINGRP_D4_200MHZ MX6QDL_USDHC3_D4(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC3_PINGRP_D8 MX6QDL_USDHC3_D8(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC3_PINGRP_D8_100MHZ MX6QDL_USDHC3_D8(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC3_PINGRP_D8_200MHZ MX6QDL_USDHC3_D8(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC4_PINGRP_D4 MX6QDL_USDHC4_D4(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC4_PINGRP_D4_100MHZ MX6QDL_USDHC4_D4(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC4_PINGRP_D4_200MHZ MX6QDL_USDHC4_D4(0x170f9,0x170f9,0x100f9)
#define MX6QDL_USDHC4_PINGRP_D8 MX6QDL_USDHC4_D8(0x17059,0x17059,0x10059)
#define MX6QDL_USDHC4_PINGRP_D8_100MHZ MX6QDL_USDHC4_D8(0x170b9,0x170b9,0x100b9)
#define MX6QDL_USDHC4_PINGRP_D8_200MHZ MX6QDL_USDHC4_D8(0x170f9,0x170f9,0x100f9)
#define MX6QDL_WEIM_CS0_PINGRP1 \
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
#define MX6QDL_WEIM_NOR_PINGRP1 \
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 \
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 \
MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 \
MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 \
MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 \
MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 \
MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 \
MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 \
MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 \
MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 \
MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 \
MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 \
MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 \
MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 \
MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 \
MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 \
MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 \
MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 \
MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 \
MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 \
MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 \
MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 \
MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 \
MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 \
MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 \
MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 \
MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 \
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 \
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 \
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 \
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 \
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 \
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 \
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 \
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 \
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 \
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 \
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 \
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 \
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 \
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 \
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 \
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
#endif /* __DTS_IMX6QDL_PINGRP_H */

379
arch/arm/dts/imx6qdl-sabrelite.dtsi
View File

@ -11,6 +11,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <arm/imx6qdl-sabrelite.dtsi>
/ {
@ -22,317 +23,20 @@
device-path = &flash, "partname:barebox-environment";
};
};
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_2p5v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
menu {
label = "Menu";
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
};
home {
label = "Home";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
};
back {
label = "Back";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
sound {
compatible = "fsl,imx6q-sabrelite-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx6q-sabrelite-sgtl5000";
ssi-controller = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <1>;
mux-ext-port = <4>;
};
backlight_lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
backlight_lvds {
compatible = "pwm-backlight";
pwms = <&pwm4 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_3p3v>;
status = "okay";
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&flash {
#address-cells = <1>;
#size-cells = <1>;
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b", "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox";
reg = <0x0 0x80000>;
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
partition@0 {
label = "barebox";
reg = <0x0 0x80000>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
txen-skew-ps = <0>;
txc-skew-ps = <3000>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <3000>;
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 201>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6q-sabrelite {
pinctrl_hog: hoggrp {
fsl,pins = <
/* SGTL5000 sys_mclk */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <MX6QDL_AUDMUX_PINGRP1>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_ECSPI1_PINGRP1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x100b0)
/* Phy reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
/* Power Button */
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
/* Menu Button */
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
/* Home Button */
MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
/* Back Button */
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
/* Volume Up Button */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
/* Volume Down Button */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP1>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_UART1_PINGRP2>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <MX6QDL_UART2_PINGRP1>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
/* power enable, high active */
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_USDHC3_PINGRP_D4
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6QDL_USDHC4_PINGRP_D4
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
>;
};
};
};
&ldb {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
};
@ -340,74 +44,11 @@
barebox,provide-mac-address = <&fec 0x620>;
};
&pcie {
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
phy_type = "utmi";
dr_mode = "host";
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
phy_type = "utmi";
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio2 6 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};

288
arch/arm/dts/imx6qdl-sabresd.dtsi
View File

@ -10,308 +10,22 @@
* http://www.gnu.org/copyleft/gpl.html
*/
/ {
memory {
reg = <0x10000000 0x40000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
reg_usb_h1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 29 0>;
enable-active-high;
};
reg_audio: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "wm8962-supply";
gpio = <&gpio4 10 0>;
enable-active-high;
};
};
gpio-keys {
compatible = "gpio-keys";
volume-up {
label = "Volume Up";
gpios = <&gpio1 4 0>;
gpio-key,wakeup;
linux,code = <115>; /* KEY_VOLUMEUP */
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 5 0>;
gpio-key,wakeup;
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};
sound {
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"MICBIAS", "AMIC",
"IN3R", "MICBIAS",
"DMIC", "MICBIAS",
"DMICDAT", "DMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
status = "okay";
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 9 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 25 0>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks 201>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0013 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
egalax_ts@04 {
compatible = "eeti,egalax_ts";
reg = <0x04>;
interrupt-parent = <&gpio6>;
interrupts = <7 2>;
wakeup-gpios = <&gpio6 7 0>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx6qdl-sabresd {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <MX6QDL_AUDMUX_PINGRP2>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <MX6QDL_ECSPI1_PINGRP2>;
};
pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_ENET_PINGRP1>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP2>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <MX6QDL_I2C3_PINGRP2>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <MX6QDL_PWM1_PINGRP1>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <MX6QDL_UART1_PINGRP1>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <MX6QDL_USBOTG_PINGRP2>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <MX6QDL_USDHC2_PINGRP_D8>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D8>;
};
};
};
&ldb {
status = "okay";
lvds-channel@1 {
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: hsd100pxn1 {
clock-frequency = <65000000>;
hactive = <1024>;
vactive = <768>;
hback-porch = <220>;
hfront-porch = <40>;
vback-porch = <21>;
vfront-porch = <7>;
hsync-len = <60>;
vsync-len = <10>;
};
};
};
};
#include <arm/imx6qdl-sabresd.dtsi>
&ocotp {
barebox,provide-mac-address = <&fec 0x620>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
phy_type = "utmi";
dr_mode = "host";
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
phy_type = "utmi";
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;

48
arch/arm/dts/imx6qdl-tqma6x.dtsi
View File

@ -32,23 +32,61 @@
&iomuxc {
imx6qdl-tqma6x {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <MX6QDL_ECSPI1_PINGRP1>;
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_ENET_PINGRP1>;
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x100b1
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x100b1
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x100b1
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x100b1
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x100b1
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x100b1
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b1
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b1
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b1
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b1
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b1
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b1
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b1
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP2>;
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <MX6QDL_I2C3_PINGRP2>;
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D8>;
fsl,pins = <
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
};
};

37
arch/arm/dts/imx6qdl-udoo.dtsi
View File

@ -88,19 +88,48 @@
};
pinctrl_enet: enetgrp {
fsl,pins = <MX6QDL_ENET_PINGRP_RGMII_MD(0x1b0b0, 0x1b0b0)>;
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <MX6QDL_I2C1_PINGRP1>;
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <MX6QDL_UART2_PINGRP1>;
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
};
};

1
arch/arm/dts/imx6qdl.dtsi
View File

@ -1,4 +1,3 @@
#include "imx6qdl-pingrp.h"
/ {
aliases {

5
arch/arm/dts/imx6s-riotboard.dts
View File

@ -72,7 +72,10 @@
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <MX6QDL_UART2_PINGRP1>;
fsl,pins = <
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_rgmii_ar8035: rgmii_ar8035 {
fsl,pins = <

18
arch/arm/mach-imx/Kconfig
View File

@ -184,6 +184,15 @@ config MACH_TX25
help
Say Y here if you are using the Ka-Ro tx25 board
config MACH_PCA100
bool "phyCard-i.MX27"
select ARCH_IMX27
select HAVE_DEFAULT_ENVIRONMENT_NEW
select ARCH_IMX_EXTERNAL_BOOT_NAND
help
Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped
with a Freescale i.MX27 Processor
config MACH_EFIKA_MX_SMARTBOOK
bool "Efika MX smartbook"
select ARCH_IMX51
@ -335,15 +344,6 @@ config MACH_IMX27ADS
Say Y here if you are using the Freescale i.MX27ads board equipped
with a Freescale i.MX27 Processor
config MACH_PCA100
bool "phyCard-i.MX27"
select ARCH_IMX27
select HAVE_DEFAULT_ENVIRONMENT_NEW
select ARCH_IMX_EXTERNAL_BOOT_NAND
help
Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped
with a Freescale i.MX27 Processor
config MACH_PCM038
bool "phyCORE-i.MX27"
select ARCH_IMX27

316
arch/arm/mach-imx/clk-imx5.c
View File

@ -16,6 +16,7 @@
#include <linux/err.h>
#include <mach/imx51-regs.h>
#include <mach/imx53-regs.h>
#include <dt-bindings/clock/imx5-clock.h>
#include "clk.h"
@ -57,20 +58,7 @@
#define CCM_CMEOR 0x84
enum imx5_clks {
dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
uart_root, esdhc_a_pred, esdhc_b_pred, esdhc_c_s, esdhc_d_s,
emi_sel, emi_slow_podf, nfc_podf, ecspi_pred, ecspi_podf, usboh3_pred,
usboh3_podf, usb_phy_pred, usb_phy_podf, cpu_podf, di_pred, lp_apm,
periph_apm, main_bus, ahb_max, aips_tz1, aips_tz2, tmax1, tmax2,
tmax3, spba, uart_sel, esdhc_a_sel, esdhc_b_sel, esdhc_a_podf,
esdhc_b_podf, ecspi_sel, usboh3_sel, usb_phy_sel,
gpc_dvfs, pll1_sw, pll2_sw,
pll3_sw, pll4_sw, per_lp_apm, per_pred1, per_pred2, per_podf, per_root,
clk_max
};
static struct clk *clks[clk_max];
static struct clk *clks[IMX5_CLK_END];
/* This is used multiple times */
static const char *standard_pll_sel[] = {
@ -125,6 +113,71 @@ static const char *usb_phy_sel_str[] = {
"usb_phy_podf",
};
static const char *mx51_ipu_di0_sel[] = {
"di_pred",
"osc",
"ckih1",
"tve_di",
};
static const char *mx53_ipu_di0_sel[] = {
"di_pred",
"osc",
"ckih1",
"di_pll4_podf",
"dummy",
"ldb_di0_div",
};
static const char *mx53_ldb_di0_sel[] = {
"pll3_sw",
"pll4_sw",
};
static const char *mx51_ipu_di1_sel[] = {
"di_pred",
"osc",
"ckih1",
"tve_di",
"ipp_di1",
};
static const char *mx53_ipu_di1_sel[] = {
"di_pred",
"osc",
"ckih1",
"tve_di",
"ipp_di1",
"ldb_di1_div",
};
static const char *mx53_ldb_di1_sel[] = {
"pll3_sw",
"pll4_sw",
};
static const char *mx51_tve_ext_sel[] = {
"osc",
"ckih1",
};
static const char *mx53_tve_ext_sel[] = {
"pll4_sw",
"ckih1",
};
static const char *mx51_tve_sel[] = {
"tve_pred",
"tve_ext_sel",
};
static const char *ipu_sel[] = {
"axi_a",
"axi_b",
"emi_slow_gate",
"ahb",
};
static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate_ckil,
unsigned long rate_osc, unsigned long rate_ckih1,
unsigned long rate_ckih2)
@ -138,89 +191,117 @@ static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate
writel(0xffffffff, base + CCM_CCGR6);
writel(0xffffffff, base + CCM_CCGR7);
clks[dummy] = clk_fixed("dummy", 0);
clks[ckil] = clk_fixed("ckil", rate_ckil);
clks[osc] = clk_fixed("osc", rate_osc);
clks[ckih1] = clk_fixed("ckih1", rate_ckih1);
clks[ckih2] = clk_fixed("ckih2", rate_ckih2);
clks[IMX5_CLK_DUMMY] = clk_fixed("dummy", 0);
clks[IMX5_CLK_CKIL] = clk_fixed("ckil", rate_ckil);
clks[IMX5_CLK_OSC] = clk_fixed("osc", rate_osc);
clks[IMX5_CLK_CKIH1] = clk_fixed("ckih1", rate_ckih1);
clks[IMX5_CLK_CKIH2] = clk_fixed("ckih2", rate_ckih2);
clks[lp_apm] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1,
clks[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
clks[periph_apm] = imx_clk_mux("periph_apm", base + CCM_CBCMR, 12, 2,
clks[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", base + CCM_CBCMR, 12, 2,
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
clks[main_bus] = imx_clk_mux("main_bus", base + CCM_CBCDR, 25, 1,
clks[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", base + CCM_CBCDR, 25, 1,
main_bus_sel, ARRAY_SIZE(main_bus_sel));
clks[per_lp_apm] = imx_clk_mux("per_lp_apm", base + CCM_CBCMR, 1, 1,
clks[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", base + CCM_CBCMR, 1, 1,
per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
clks[per_pred1] = imx_clk_divider("per_pred1", "per_lp_apm", base + CCM_CBCDR, 6, 2);
clks[per_pred2] = imx_clk_divider("per_pred2", "per_pred1", base + CCM_CBCDR, 3, 3);
clks[per_podf] = imx_clk_divider("per_podf", "per_pred2", base + CCM_CBCDR, 0, 3);
clks[per_root] = imx_clk_mux("per_root", base + CCM_CBCMR, 0, 1,
clks[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", base + CCM_CBCDR, 6, 2);
clks[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", base + CCM_CBCDR, 3, 3);
clks[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", base + CCM_CBCDR, 0, 3);
clks[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", base + CCM_CBCMR, 0, 1,
per_root_sel, ARRAY_SIZE(per_root_sel));
clks[ahb] = imx_clk_divider("ahb", "main_bus", base + CCM_CBCDR, 10, 3);
clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_CBCDR, 8, 2);
clks[axi_a] = imx_clk_divider("axi_a", "main_bus", base + CCM_CBCDR, 16, 3);
clks[axi_b] = imx_clk_divider("axi_b", "main_bus", base + CCM_CBCDR, 19, 3);
clks[uart_sel] = imx_clk_mux("uart_sel", base + CCM_CSCMR1, 24, 2,
clks[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", base + CCM_CBCDR, 10, 3);
clks[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + CCM_CBCDR, 8, 2);
clks[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", base + CCM_CBCDR, 16, 3);
clks[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", base + CCM_CBCDR, 19, 3);
clks[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + CCM_CSCMR1, 24, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[uart_pred] = imx_clk_divider("uart_pred", "uart_sel", base + CCM_CSCDR1, 3, 3);
clks[uart_root] = imx_clk_divider("uart_root", "uart_pred", base + CCM_CSCDR1, 0, 3);
clks[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", base + CCM_CSCDR1, 3, 3);
clks[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", base + CCM_CSCDR1, 0, 3);
clks[esdhc_a_sel] = imx_clk_mux("esdhc_a_sel", base + CCM_CSCMR1, 20, 2,
clks[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", base + CCM_CSCMR1, 20, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[esdhc_b_sel] = imx_clk_mux("esdhc_b_sel", base + CCM_CSCMR1, 16, 2,
clks[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", base + CCM_CSCMR1, 16, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[esdhc_a_pred] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", base + CCM_CSCDR1, 16, 3);
clks[esdhc_a_podf] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", base + CCM_CSCDR1, 11, 3);
clks[esdhc_b_pred] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", base + CCM_CSCDR1, 22, 3);
clks[esdhc_b_podf] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", base + CCM_CSCDR1, 19, 3);
clks[esdhc_c_s] = imx_clk_mux("esdhc_c_sel", base + CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
clks[esdhc_d_s] = imx_clk_mux("esdhc_d_sel", base + CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
clks[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", base + CCM_CSCDR1, 16, 3);
clks[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", base + CCM_CSCDR1, 11, 3);
clks[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", base + CCM_CSCDR1, 22, 3);
clks[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", base + CCM_CSCDR1, 19, 3);
clks[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", base + CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
clks[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", base + CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
clks[emi_sel] = imx_clk_mux("emi_sel", base + CCM_CBCDR, 26, 1,
clks[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", base + CCM_CBCDR, 26, 1,
emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
clks[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_sel", base + CCM_CBCDR, 22, 3);
clks[nfc_podf] = imx_clk_divider("nfc_podf", "emi_slow_podf", base + CCM_CBCDR, 13, 3);
clks[ecspi_sel] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1, 4, 2,
clks[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", base + CCM_CBCDR, 22, 3);
clks[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", base + CCM_CBCDR, 13, 3);
clks[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + CCM_CSCMR1, 4, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[ecspi_pred] = imx_clk_divider("ecspi_pred", "ecspi_sel", base + CCM_CSCDR2, 25, 3);
clks[ecspi_podf] = imx_clk_divider("ecspi_podf", "ecspi_pred", base + CCM_CSCDR2, 19, 6);
clks[usboh3_sel] = imx_clk_mux("usboh3_sel", base + CCM_CSCMR1, 22, 2,
clks[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", base + CCM_CSCDR2, 25, 3);
clks[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", base + CCM_CSCDR2, 19, 6);
clks[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", base + CCM_CSCMR1, 22, 2,
standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
clks[usboh3_pred] = imx_clk_divider("usboh3_pred", "usboh3_sel", base + CCM_CSCDR1, 8, 3);
clks[usboh3_podf] = imx_clk_divider("usboh3_podf", "usboh3_pred", base + CCM_CSCDR1, 6, 2);
clks[usb_phy_pred] = imx_clk_divider("usb_phy_pred", "pll3_sw", base + CCM_CDCDR, 3, 3);
clks[usb_phy_podf] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3);
clks[usb_phy_sel] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1,
clks[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", base + CCM_CSCDR1, 8, 3);
clks[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", base + CCM_CSCDR1, 6, 2);
clks[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", base + CCM_CDCDR, 3, 3);
clks[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", base + CCM_CDCDR, 0, 3);
clks[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", base + CCM_CSCMR1, 26, 1,
usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
clks[cpu_podf] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3);
clks[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "pll1_sw", base + CCM_CACRR, 0, 3);
}
static void mx5_clocks_ipu_init(void __iomem *regs)
{
clks[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", regs + CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
}
static void mx51_clocks_ipu_init(void __iomem *regs)
{
clks[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_p("ipu_di0_sel", regs + CCM_CSCMR2, 26, 3,
mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
clks[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_p("ipu_di1_sel", regs + CCM_CSCMR2, 29, 3,
mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
clks[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_p("tve_ext_sel", regs + CCM_CSCMR1, 6, 1,
mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel));
clks[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", regs + CCM_CSCMR1, 7, 1,
mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
clks[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", regs + CCM_CDCDR, 28, 3);
mx5_clocks_ipu_init(regs);
clkdev_add_physbase(clks[IMX5_CLK_IPU_SEL], MX51_IPU_BASE_ADDR, "bus");
clkdev_add_physbase(clks[IMX5_CLK_IPU_DI0_SEL], MX51_IPU_BASE_ADDR, "di0");
clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX51_IPU_BASE_ADDR, "di1");
}
#ifdef CONFIG_ARCH_IMX51
int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
unsigned long rate_ckih1, unsigned long rate_ckih2)
{
clks[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR);
clks[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR);
clks[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL3_BASE_ADDR);
clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR);
clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR);
clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL3_BASE_ADDR);
mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
clkdev_add_physbase(clks[uart_root], MX51_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[uart_root], MX51_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[uart_root], MX51_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per_root], MX51_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per_root], MX51_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per_root], MX51_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX51_CSPI_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ecspi_podf], MX51_ECSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ecspi_podf], MX51_ECSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX51_MXC_FEC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[esdhc_a_podf], MX51_MMC_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[esdhc_b_podf], MX51_MMC_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[esdhc_c_s], MX51_MMC_SDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[esdhc_d_s], MX51_MMC_SDHC4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX51_ATA_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_CSPI_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX51_ECSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX51_ECSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_MXC_FEC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_A_PODF], MX51_MMC_SDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_B_PODF], MX51_MMC_SDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_C_SEL], MX51_MMC_SDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX51_MMC_SDHC4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_IPG], MX51_ATA_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM1_BASE_ADDR, "per");
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX51_PWM2_BASE_ADDR, "per");
if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
mx51_clocks_ipu_init(regs);
return 0;
}
@ -250,40 +331,63 @@ static struct driver_d imx51_ccm_driver = {
.of_compatible = DRV_OF_COMPAT(imx51_ccm_dt_ids),
};
static int imx51_ccm_init(void)
static void mx53_clocks_ipu_init(void __iomem *regs)
{
return platform_driver_register(&imx51_ccm_driver);
}
core_initcall(imx51_ccm_init);
#endif
clks[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
clks[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", regs + CCM_CSCMR2, 11, 1);
clks[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", regs + CCM_CSCMR2, 9, 1,
mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
clks[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", regs + CCM_CDCDR, 16, 3);
clks[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
clks[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider("ldb_di0_div", "ldb_di0_div_3_5", regs + CCM_CSCMR2, 10, 1);
clks[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel", regs + CCM_CSCMR2, 8, 1,
mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel));
clks[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux_p("ipu_di0_sel", regs + CCM_CSCMR2, 26, 3,
mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
clks[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux_p("ipu_di1_sel", regs + CCM_CSCMR2, 29, 3,
mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
clks[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_p("tve_ext_sel", regs + CCM_CSCMR1, 6, 1,
mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel));
clks[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", regs + CCM_CDCDR, 28, 3);
mx5_clocks_ipu_init(regs);
clkdev_add_physbase(clks[IMX5_CLK_IPU_SEL], MX53_IPU_BASE_ADDR, "bus");
clkdev_add_physbase(clks[IMX5_CLK_IPU_DI0_SEL], MX53_IPU_BASE_ADDR, "di0");
clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX53_IPU_BASE_ADDR, "di1");
}
#ifdef CONFIG_ARCH_IMX53
int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
unsigned long rate_ckih1, unsigned long rate_ckih2)
{
clks[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX53_PLL1_BASE_ADDR);
clks[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX53_PLL2_BASE_ADDR);
clks[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX53_PLL3_BASE_ADDR);
clks[pll4_sw] = imx_clk_pllv2("pll4_sw", "osc", (void *)MX53_PLL4_BASE_ADDR);
clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX53_PLL1_BASE_ADDR);
clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX53_PLL2_BASE_ADDR);
clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX53_PLL3_BASE_ADDR);
clks[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", (void *)MX53_PLL4_BASE_ADDR);
mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
clkdev_add_physbase(clks[uart_root], MX53_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[uart_root], MX53_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[uart_root], MX53_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per_root], MX53_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per_root], MX53_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per_root], MX53_I2C3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[per_root], MX53_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX53_CSPI_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ecspi_podf], MX53_ECSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ecspi_podf], MX53_ECSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ipg], MX53_FEC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[esdhc_a_podf], MX53_ESDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[esdhc_c_s], MX53_ESDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[esdhc_b_podf], MX53_ESDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[esdhc_d_s], MX53_ESDHC4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[ahb], MX53_SATA_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_I2C3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_GPT1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_IPG], MX53_CSPI_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX53_ECSPI1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ECSPI_PODF], MX53_ECSPI2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_IPG], MX53_FEC_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_A_PODF], MX53_ESDHC1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_C_SEL], MX53_ESDHC2_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_B_PODF], MX53_ESDHC3_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_ESDHC_D_SEL], MX53_ESDHC4_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_AHB], MX53_SATA_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM1_BASE_ADDR, "per");
clkdev_add_physbase(clks[IMX5_CLK_PER_ROOT], MX53_PWM2_BASE_ADDR, "per");
if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
mx53_clocks_ipu_init(regs);
return 0;
}
@ -313,9 +417,13 @@ static struct driver_d imx53_ccm_driver = {
.of_compatible = DRV_OF_COMPAT(imx53_ccm_dt_ids),
};
static int imx53_ccm_init(void)
static int imx5_ccm_init(void)
{
return platform_driver_register(&imx53_ccm_driver);
if (IS_ENABLED(CONFIG_ARCH_IMX51))
platform_driver_register(&imx51_ccm_driver);
if (IS_ENABLED(CONFIG_ARCH_IMX53))
platform_driver_register(&imx53_ccm_driver);
return 0;
}
core_initcall(imx53_ccm_init);
#endif
core_initcall(imx5_ccm_init);

66
arch/arm/mach-imx/clk-pllv2.c
View File

@ -136,8 +136,74 @@ static unsigned long clk_pllv2_recalc_rate(struct clk *clk,
return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
}
static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn)
{
u32 reg;
long mfi, pdf, mfn, mfd = 999999;
u64 temp64;
unsigned long quad_parent_rate;
quad_parent_rate = 4 * parent_rate;
pdf = mfi = -1;
while (++pdf < 16 && mfi < 5)
mfi = rate * (pdf+1) / quad_parent_rate;
if (mfi > 15)
return -EINVAL;
pdf--;
temp64 = rate * (pdf + 1) - quad_parent_rate * mfi;
do_div(temp64, quad_parent_rate / 1000000);
mfn = (long)temp64;
reg = mfi << 4 | pdf;
*dp_op = reg;
*dp_mfd = mfd;
*dp_mfn = mfn;
return 0;
}
static int clk_pllv2_set_rate(struct clk *clk, unsigned long rate,
unsigned long parent_rate)
{
struct clk_pllv2 *pll = container_of(clk, struct clk_pllv2, clk);
void __iomem *pllbase;
u32 dp_ctl, dp_op, dp_mfd, dp_mfn;
int ret;
pllbase = pll->reg;
ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn);
if (ret)
return ret;
dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
/* use dpdck0_2 */
__raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
__raw_writel(dp_op, pllbase + MXC_PLL_DP_OP);
__raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD);
__raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN);
return 0;
}
static long clk_pllv2_round_rate(struct clk *clk, unsigned long rate,
unsigned long *prate)
{
u32 dp_op, dp_mfd, dp_mfn;
__clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
dp_op, dp_mfd, dp_mfn);
}
struct clk_ops clk_pllv2_ops = {
.recalc_rate = clk_pllv2_recalc_rate,
.round_rate = clk_pllv2_round_rate,
.set_rate = clk_pllv2_set_rate,
};
struct clk *imx_clk_pllv2(const char *name, const char *parent,

271
arch/arm/mach-imx/imx-bbu-internal.c
View File

@ -40,9 +40,6 @@
struct imx_internal_bbu_handler {
struct bbu_handler handler;
const void *dcd;
int dcdsize;
unsigned long app_dest;
unsigned long flash_header_offset;
size_t device_size;
unsigned long flags;
@ -130,13 +127,7 @@ static int imx_bbu_internal_v1_update(struct bbu_handler *handler, struct bbu_da
{
struct imx_internal_bbu_handler *imx_handler =
container_of(handler, struct imx_internal_bbu_handler, handler);
struct imx_flash_header *flash_header;
unsigned long flash_header_offset = imx_handler->flash_header_offset;
u32 *dcd_image_size;
void *imx_pre_image;
int imx_pre_image_size = 0x2000;
int ret, image_len;
void *buf;
int ret;
ret = imx_bbu_check_prereq(data);
if (ret)
@ -144,38 +135,7 @@ static int imx_bbu_internal_v1_update(struct bbu_handler *handler, struct bbu_da
printf("updating to %s\n", data->devicefile);
imx_pre_image = xzalloc(imx_pre_image_size);
flash_header = imx_pre_image + flash_header_offset;
flash_header->app_code_jump_vector = imx_handler->app_dest + 0x1000;
flash_header->app_code_barker = APP_CODE_BARKER;
flash_header->app_code_csf = 0;
flash_header->dcd_ptr_ptr = imx_handler->app_dest + flash_header_offset +
offsetof(struct imx_flash_header, dcd);
flash_header->super_root_key = 0;
flash_header->dcd = imx_handler->app_dest + flash_header_offset +
offsetof(struct imx_flash_header, dcd_barker);
flash_header->app_dest = imx_handler->app_dest;
flash_header->dcd_barker = DCD_BARKER;
flash_header->dcd_block_len = imx_handler->dcdsize;
memcpy((void *)flash_header + sizeof(*flash_header), imx_handler->dcd, imx_handler->dcdsize);
dcd_image_size = (imx_pre_image + flash_header_offset + sizeof(*flash_header) + imx_handler->dcdsize);
*dcd_image_size = ALIGN(imx_pre_image_size + data->len, 4096);
/* Create a buffer containing header and image data */
image_len = data->len + imx_pre_image_size;
buf = xzalloc(image_len);
memcpy(buf, imx_pre_image, imx_pre_image_size);
memcpy(buf + imx_pre_image_size, data->image, data->len);
ret = imx_bbu_write_device(imx_handler, data, buf, image_len);
free(buf);
free(imx_pre_image);
ret = imx_bbu_write_device(imx_handler, data, data->image, data->len);
return ret;
}
@ -337,43 +297,6 @@ out:
return ret;
}
static void imx_bbu_internal_v2_init_flash_header(struct bbu_handler *handler, struct bbu_data *data,
void *imx_pre_image, int imx_pre_image_size)
{
struct imx_internal_bbu_handler *imx_handler =
container_of(handler, struct imx_internal_bbu_handler, handler);
struct imx_flash_header_v2 *flash_header;
unsigned long flash_header_offset = imx_handler->flash_header_offset;
flash_header = imx_pre_image + flash_header_offset;
flash_header->header.tag = IVT_HEADER_TAG;
flash_header->header.length = cpu_to_be16(32);
flash_header->header.version = IVT_VERSION;
flash_header->entry = imx_handler->app_dest + imx_pre_image_size;
if (imx_handler->dcdsize)
flash_header->dcd_ptr = imx_handler->app_dest + flash_header_offset +
offsetof(struct imx_flash_header_v2, dcd);
flash_header->boot_data_ptr = imx_handler->app_dest +
flash_header_offset + offsetof(struct imx_flash_header_v2, boot_data);
flash_header->self = imx_handler->app_dest + flash_header_offset;
flash_header->boot_data.start = imx_handler->app_dest;
flash_header->boot_data.size = ALIGN(imx_pre_image_size +
data->len, 4096);
if (imx_handler->dcdsize) {
flash_header->dcd.header.tag = DCD_HEADER_TAG;
flash_header->dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) +
imx_handler->dcdsize);
flash_header->dcd.header.version = DCD_VERSION;
}
/* Add dcd data */
memcpy((void *)flash_header + sizeof(*flash_header), imx_handler->dcd, imx_handler->dcdsize);
}
#define IVT_BARKER 0x402000d1
/*
@ -391,84 +314,43 @@ static int imx_bbu_internal_v2_update(struct bbu_handler *handler, struct bbu_da
int imx_pre_image_size;
int ret, image_len;
void *buf;
uint32_t *barker;
ret = imx_bbu_check_prereq(data);
if (ret)
return ret;
if (imx_handler->dcd) {
imx_pre_image_size = 0x2000;
} else {
uint32_t *barker = data->image + imx_handler->flash_header_offset;
barker = data->image + imx_handler->flash_header_offset;
if (*barker != IVT_BARKER) {
printf("Board does not provide DCD data and this image is no imximage\n");
return -EINVAL;
}
imx_pre_image_size = 0;
if (*barker != IVT_BARKER) {
printf("Board does not provide DCD data and this image is no imximage\n");
return -EINVAL;
}
if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND)
/* NAND needs additional space for the DBBT */
imx_pre_image_size += 0x6000;
if (imx_pre_image_size)
imx_pre_image = xzalloc(imx_pre_image_size);
if (imx_handler->dcd)
imx_bbu_internal_v2_init_flash_header(handler, data, imx_pre_image, imx_pre_image_size);
/* Create a buffer containing header and image data */
image_len = data->len + imx_pre_image_size;
buf = xzalloc(image_len);
if (imx_pre_image_size)
memcpy(buf, imx_pre_image, imx_pre_image_size);
memcpy(buf + imx_pre_image_size, data->image, data->len);
imx_pre_image_size = 0;
if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND) {
/* NAND needs additional space for the DBBT */
imx_pre_image_size += 0x6000;
imx_pre_image = xzalloc(imx_pre_image_size);
/* Create a buffer containing header and image data */
image_len = data->len + imx_pre_image_size;
buf = xzalloc(image_len);
memcpy(buf, imx_pre_image, imx_pre_image_size);
memcpy(buf + imx_pre_image_size, data->image, data->len);
ret = imx_bbu_internal_v2_write_nand_dbbt(imx_handler, data, buf,
image_len);
goto out_free_buf;
free(buf);
free(imx_pre_image);
} else {
ret = imx_bbu_write_device(imx_handler, data, data->image, data->len);
}
ret = imx_bbu_write_device(imx_handler, data, buf, image_len);
out_free_buf:
free(buf);
free(imx_pre_image);
return ret;
}
/*
* On the i.MX53 the dcd data can contain several commands. Each of them must
* have its length encoded into it. We can't express that during compile time,
* so use this function if you are using multiple dcd commands and wish to
* concatenate them together to a single dcd table with the correct sizes for
* each command.
*/
void *imx53_bbu_internal_concat_dcd_table(struct dcd_table *table, int num_entries)
{
int i;
unsigned int dcdsize = 0, pos = 0;
void *dcdptr;
for (i = 0; i < num_entries; i++)
dcdsize += table[i].size;
dcdptr = xmalloc(dcdsize);
for (i = 0; i < num_entries; i++) {
u32 *current = dcdptr + pos;
memcpy(current, table[i].data, table[i].size);
*current |= cpu_to_be32(table[i].size << 8);
pos += table[i].size;
}
return dcdptr;
}
static struct imx_internal_bbu_handler *__init_handler(const char *name, char *devicefile,
unsigned long flags)
{
@ -499,87 +381,30 @@ static int __register_handler(struct imx_internal_bbu_handler *imx_handler)
* Register a i.MX51 internal boot update handler for MMC/SD
*/
int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_entry *dcd, int dcdsize,
unsigned long app_dest)
unsigned long flags)
{
struct imx_internal_bbu_handler *imx_handler;
imx_handler = __init_handler(name, devicefile, flags);
imx_handler->dcd = dcd;
imx_handler->dcdsize = dcdsize;
imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
if (app_dest)
imx_handler->app_dest = app_dest;
else
imx_handler->app_dest = 0x90000000;
imx_handler->flags = IMX_INTERNAL_FLAG_KEEP_DOSPART;
imx_handler->handler.handler = imx_bbu_internal_v1_update;
return __register_handler(imx_handler);
}
#define DCD_WR_CMD(len) cpu_to_be32(0xcc << 24 | (((len) & 0xffff) << 8) | 0x04)
static int imx53_bbu_internal_init_dcd(struct imx_internal_bbu_handler *imx_handler,
void *dcd, int dcdsize)
{
uint32_t *dcd32 = dcd;
/*
* For boards which do not have a dcd (i.e. they do their SDRAM
* setup in C code)
*/
if (!dcd || !dcdsize)
return 0;
/*
* The DCD data we have compiled in does not have a DCD_WR_CMD at
* the beginning. Instead it is contained in struct imx_flash_header_v2.
* This is necessary to generate the DCD size at compile time. If
* we are passed such a DCD data here, prepend a DCD_WR_CMD.
*/
if ((*dcd32 & 0xff0000ff) != DCD_WR_CMD(0)) {
__be32 *buf;
debug("%s: dcd does not have a DCD_WR_CMD. Prepending one\n", __func__);
buf = xmalloc(dcdsize + sizeof(__be32));
*buf = DCD_WR_CMD(dcdsize + sizeof(__be32));
memcpy(&buf[1], dcd, dcdsize);
imx_handler->dcd = buf;
imx_handler->dcdsize = dcdsize + sizeof(__be32);
} else {
debug("%s: dcd already has a DCD_WR_CMD. Using original dcd data\n", __func__);
imx_handler->dcd = dcd;
imx_handler->dcdsize = dcdsize;
}
return 0;
}
/*
* Register a i.MX53 internal boot update handler for MMC/SD
*/
int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
unsigned long app_dest)
unsigned long flags)
{
struct imx_internal_bbu_handler *imx_handler;
imx_handler = __init_handler(name, devicefile, flags);
imx53_bbu_internal_init_dcd(imx_handler, dcd, dcdsize);
imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
if (app_dest)
imx_handler->app_dest = app_dest;
else
imx_handler->app_dest = 0x70000000;
imx_handler->flags = IMX_INTERNAL_FLAG_KEEP_DOSPART;
imx_handler->handler.handler = imx_bbu_internal_v2_update;
@ -592,20 +417,13 @@ int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
* keep a partition table. We have to erase the device beforehand though.
*/
int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
unsigned long app_dest)
unsigned long flags)
{
struct imx_internal_bbu_handler *imx_handler;
imx_handler = __init_handler(name, devicefile, flags);
imx53_bbu_internal_init_dcd(imx_handler, dcd, dcdsize);
imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
if (app_dest)
imx_handler->app_dest = app_dest;
else
imx_handler->app_dest = 0x70000000;
imx_handler->flags = IMX_INTERNAL_FLAG_ERASE;
imx_handler->handler.handler = imx_bbu_internal_v2_update;
@ -616,20 +434,13 @@ int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefi
* Register a i.MX53 internal boot update handler for NAND
*/
int imx53_bbu_internal_nand_register_handler(const char *name,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
int partition_size, unsigned long app_dest)
unsigned long flags, int partition_size)
{
struct imx_internal_bbu_handler *imx_handler;
imx_handler = __init_handler(name, NULL, flags);
imx53_bbu_internal_init_dcd(imx_handler, dcd, dcdsize);
imx_handler->flash_header_offset = 0x400;
if (app_dest)
imx_handler->app_dest = app_dest;
else
imx_handler->app_dest = 0x70000000;
imx_handler->handler.handler = imx_bbu_internal_v2_update;
imx_handler->flags = IMX_INTERNAL_FLAG_NAND;
imx_handler->handler.devicefile = "/dev/nand0";
@ -642,14 +453,17 @@ int imx53_bbu_internal_nand_register_handler(const char *name,
* Register a i.MX6 internal boot update handler for MMC/SD
*/
int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
unsigned long app_dest)
unsigned long flags)
{
if (!app_dest)
app_dest = 0x10000000;
struct imx_internal_bbu_handler *imx_handler;
return imx53_bbu_internal_mmc_register_handler(name, devicefile,
flags, dcd, dcdsize, app_dest);
imx_handler = __init_handler(name, devicefile, flags);
imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
imx_handler->flags = IMX_INTERNAL_FLAG_KEEP_DOSPART;
imx_handler->handler.handler = imx_bbu_internal_v2_update;
return __register_handler(imx_handler);
}
/*
@ -658,12 +472,15 @@ int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
* keep a partition table. We have to erase the device beforehand though.
*/
int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
unsigned long app_dest)
unsigned long flags)
{
if (!app_dest)
app_dest = 0x10000000;
struct imx_internal_bbu_handler *imx_handler;
return imx53_bbu_internal_spi_i2c_register_handler(name, devicefile,
flags, dcd, dcdsize, app_dest);
imx_handler = __init_handler(name, devicefile, flags);
imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC;
imx_handler->flags = IMX_INTERNAL_FLAG_ERASE;
imx_handler->handler.handler = imx_bbu_internal_v2_update;
return __register_handler(imx_handler);
}

43
arch/arm/mach-imx/include/mach/bbu.h
View File

@ -10,71 +10,59 @@ struct imx_dcd_v2_entry;
#ifdef CONFIG_BAREBOX_UPDATE
int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_entry *, int dcdsize,
unsigned long app_dest);
unsigned long flags);
int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *, int dcdsize,
unsigned long app_dest);
unsigned long flags);
int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
unsigned long app_dest);
unsigned long flags);
int imx53_bbu_internal_nand_register_handler(const char *name,
unsigned long flags, struct imx_dcd_v2_entry *, int dcdsize,
int partition_size, unsigned long app_dest);
unsigned long flags, int partition_size);
int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *, int dcdsize,
unsigned long app_dest);
unsigned long flags);
int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
unsigned long app_dest);
unsigned long flags);
int imx6_bbu_nand_register_handler(const char *name, unsigned long flags);
#else
static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_entry *dcd, int dcdsize,
unsigned long app_dest)
unsigned long flags)
{
return -ENOSYS;
}
static inline int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
unsigned long app_dest)
unsigned long flags)
{
return -ENOSYS;
}
static inline int imx53_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
unsigned long app_dest)
unsigned long flags)
{
return -ENOSYS;
}
static inline int imx53_bbu_internal_nand_register_handler(const char *name,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
int partition_size, unsigned long app_dest)
unsigned long flags, int partition_size)
{
return -ENOSYS;
}
static inline int imx6_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
unsigned long app_dest)
unsigned long flags)
{
return -ENOSYS;
}
static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize,
unsigned long app_dest)
unsigned long flags)
{
return -ENOSYS;
}
@ -96,11 +84,4 @@ static inline int imx_bbu_external_nand_register_handler(const char *name, char
}
#endif
struct dcd_table {
void *data;
unsigned int size;
};
void *imx53_bbu_internal_concat_dcd_table(struct dcd_table *table, int num_entries);
#endif

2
arch/arm/mach-imx/include/mach/imx51-regs.h
View File

@ -13,6 +13,8 @@
#define MX51_IROM_BASE_ADDR 0x0
#define MX51_IPU_BASE_ADDR 0x40000000
/*
* AIPS 1
*/

1
arch/arm/mach-imx/include/mach/imx53-regs.h
View File

@ -5,6 +5,7 @@
#define MX53_SATA_BASE_ADDR 0x10000000
#define MX53_IPU_BASE_ADDR 0x18000000
/*
* SPBA global module enabled #0
*/

50
drivers/mfd/mc13xxx.c
View File

@ -60,6 +60,21 @@ int mc13xxx_revision(struct mc13xxx *mc13xxx)
}
EXPORT_SYMBOL(mc13xxx_revision);
static void(*mc13xxx_init_callback)(struct mc13xxx *mc13xxx);
int mc13xxx_register_init_callback(void(*callback)(struct mc13xxx *mc13xxx))
{
if (mc13xxx_init_callback)
return -EBUSY;
mc13xxx_init_callback = callback;
if (mc_dev)
mc13xxx_init_callback(mc_dev);
return 0;
}
#ifdef CONFIG_SPI
static int spi_rw(struct spi_device *spi, void * buf, size_t len)
{
@ -350,6 +365,9 @@ static int __init mc13xxx_probe(struct device_d *dev)
mc_dev->revision = rev;
devfs_create(&mc_dev->cdev);
if (mc13xxx_init_callback)
mc13xxx_init_callback(mc_dev);
return 0;
}
@ -379,7 +397,6 @@ static __maybe_unused struct of_device_id mc13xxx_dt_ids[] = {
{ }
};
#ifdef CONFIG_I2C
static struct driver_d mc13xxx_i2c_driver = {
.name = "mc13xxx-i2c",
.probe = mc13xxx_probe,
@ -387,19 +404,30 @@ static struct driver_d mc13xxx_i2c_driver = {
.of_compatible = DRV_OF_COMPAT(mc13xxx_dt_ids),
};
static int __init mc13xxx_i2c_init(void)
{
return i2c_driver_register(&mc13xxx_i2c_driver);
}
device_initcall(mc13xxx_i2c_init);
#endif
#ifdef CONFIG_SPI
static struct driver_d mc13xxx_spi_driver = {
.name = "mc13xxx-spi",
.probe = mc13xxx_probe,
.id_table = mc13xxx_ids,
.of_compatible = DRV_OF_COMPAT(mc13xxx_dt_ids),
};
device_spi_driver(mc13xxx_spi_driver);
#endif
static int __init mc13xxx_init(void)
{
int err_spi = 0, err_i2c = 0;
if (IS_ENABLED(CONFIG_I2C))
err_spi = i2c_driver_register(&mc13xxx_i2c_driver);
if (IS_ENABLED(CONFIG_SPI))
err_i2c = spi_driver_register(&mc13xxx_spi_driver);
if (err_spi)
return err_spi;
if (err_i2c)
return err_i2c;
return 0;
}
coredevice_initcall(mc13xxx_init);

3
drivers/pinctrl/imx-iomux-v3.c
View File

@ -117,7 +117,8 @@ static int imx_iomux_v3_set_state(struct pinctrl_device *pdev, struct device_nod
if (!size || size % FSL_PIN_SIZE) {
dev_err(iomux->pinctrl.dev, "Invalid fsl,pins property\n");
dev_err(iomux->pinctrl.dev, "Invalid fsl,pins property in %s\n",
np->full_name);
return -EINVAL;
}

2
drivers/spi/imx_spi.c
View File

@ -586,4 +586,4 @@ static struct driver_d imx_spi_driver = {
.of_compatible = DRV_OF_COMPAT(imx_spi_dt_ids),
.id_table = imx_spi_ids,
};
device_platform_driver(imx_spi_driver);
coredevice_platform_driver(imx_spi_driver);

31
drivers/video/imx-ipu-v3/imx-ldb.c
View File

@ -190,7 +190,36 @@ static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
static int imx53_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
{
return -ENOSYS;
struct clk *diclk, *ldbclk;
struct imx_ldb *ldb = imx_ldb_ch->ldb;
int ret, dino;
char *clkname;
dino = di & 0x1;
clkname = asprintf("ipu_di%d_sel", dino);
diclk = clk_lookup(clkname);
free(clkname);
if (IS_ERR(diclk)) {
dev_err(ldb->dev, "failed to get di clk: %s\n", strerror(PTR_ERR(diclk)));
return PTR_ERR(diclk);
}
clkname = asprintf("ldb_di%d_div", imx_ldb_ch->chno);
ldbclk = clk_lookup(clkname);
free(clkname);
if (IS_ERR(ldbclk)) {
dev_err(ldb->dev, "failed to get ldb clk: %s\n", strerror(PTR_ERR(ldbclk)));
return PTR_ERR(ldbclk);
}
ret = clk_set_parent(diclk, ldbclk);
if (ret) {
dev_err(ldb->dev, "failed to set display clock parent: %s\n", strerror(-ret));
return ret;
}
return 0;
}
static struct imx_ldb_data imx_ldb_data_imx6q = {

29
drivers/video/imx-ipu-v3/ipu-common.c
View File

@ -22,6 +22,8 @@
#include <asm/mmu.h>
#include <mach/generic.h>
#include <mach/imx6-regs.h>
#include <mach/imx53-regs.h>
#include <mach/imx51-regs.h>
#include "imx-ipu-v3.h"
#include "ipu-prv.h"
@ -529,6 +531,31 @@ static int imx6_ipu_reset(struct ipu_soc *ipu)
}
static int imx5_ipu_reset(void __iomem *src_base)
{
uint32_t val;
int ret;
val = ipureadl(src_base);
val |= (1 << 3);
ipuwritel("reset", val, src_base);
ret = wait_on_timeout(100 * MSECOND, !(readl(src_base) & (1 << 3)));
return ret;
}
static int imx51_ipu_reset(struct ipu_soc *ipu)
{
return imx5_ipu_reset((void *)MX51_SRC_BASE_ADDR);
}
static int imx53_ipu_reset(struct ipu_soc *ipu)
{
return imx5_ipu_reset((void *)MX53_SRC_BASE_ADDR);
}
struct ipu_devtype {
const char *name;
unsigned long cm_ofs;
@ -554,6 +581,7 @@ static struct ipu_devtype ipu_type_imx51 = {
.dc_tmpl_ofs = 0x1f080000,
.vdi_ofs = 0x1e068000,
.type = IPUV3EX,
.reset = imx51_ipu_reset,
};
static struct ipu_devtype ipu_type_imx53 = {
@ -567,6 +595,7 @@ static struct ipu_devtype ipu_type_imx53 = {
.dc_tmpl_ofs = 0x07080000,
.vdi_ofs = 0x06068000,
.type = IPUV3M,
.reset = imx53_ipu_reset,
};
static struct ipu_devtype ipu_type_imx6q = {

4
images/Makefile.imx
View File

@ -19,6 +19,10 @@ CFG_start_imx25_karo_tx25.pblx.imximg = $(board)/karo-tx25/flash-header-tx25.imx
FILE_barebox-karo-tx25-internal.img = start_imx25_karo_tx25.pblx.imximg
image-$(CONFIG_MACH_TX25) += barebox-karo-tx25-internal.img
pblx-$(CONFIG_MACH_PCA100) += start_phytec_phycard_imx27
FILE_barebox-phytec-phycard-imx27.img = start_phytec_phycard_imx27.pblx
image-$(CONFIG_MACH_PCA100) += barebox-phytec-phycard-imx27.img
# ----------------------- i.MX51 based boards ---------------------------
pblx-$(CONFIG_MACH_FREESCALE_MX51_PDK) += start_imx51_babbage
CFG_start_imx51_babbage.pblx.imximg = $(board)/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg

6
include/mfd/mc13xxx.h
View File

@ -171,6 +171,7 @@ extern int mc13xxx_revision(struct mc13xxx *mc13xxx);
extern int mc13xxx_reg_read(struct mc13xxx *mc13xxx, u8 reg, u32 *val);
extern int mc13xxx_reg_write(struct mc13xxx *mc13xxx, u8 reg, u32 val);
extern int mc13xxx_set_bits(struct mc13xxx *mc13xxx, u8 reg, u32 mask, u32 val);
int mc13xxx_register_init_callback(void(*callback)(struct mc13xxx *mc13xxx));
#else
static inline struct mc13xxx *mc13xxx_get(void)
{
@ -196,6 +197,11 @@ static inline int mc13xxx_set_bits(struct mc13xxx *mc13xxx, u8 reg, u32 mask, u3
{
return -ENODEV;
}
static inline int mc13xxx_register_init_callback(void(*callback)(struct mc13xxx *mc13xxx))
{
return -ENODEV;
}
#endif
#endif /* __MFD_MC13XXX_H */