Move PIT driver code to 'drivers/clocsource' and accomodate it by
adjusting Kconfig variables. Rename the file to 'timer-atmel-pit.c' to
re-align the driver with code in Linux kernel.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Use VERSION register instead of CPU type to determine IP block's version
and capabilities. This what corresponding Linux kernel driver does.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On AT91 GPIOs default to being inputs, so we need to explicitly
configure CS gpio to being an output.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Zero ehci_data before using it as an argument for echi_register,
otherwise bogus values (some of which are interpreted as callbacks) will
be passed through, resulting in illegal memory accesses.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Store driver data in per-device private variable as opposed to storing
it in global vairables.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Port Linux kernel algorithm for both of_device_is_compatible() and
of_match_node(). With this change former now returns a score on the
scale of 0 to INT_MAX/2, and the latter goes through all compatiblity
entries and selects the entry that has the best matching score.
This is needed for SoCs where IP blocks are backwards compatible and
corresponding OF nodes can proclaim compatibility with several entries
found in driver's compatiblity table. One such example would be PIO
pinctrl block on AT91SAM9x5 SoCs which declare compatibility with with
both "atmel,at91sam9x5-pinctrl" and "atmel,at91rm9200-pinctrl".
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since fc10539f7d the usbmisc pointer must be stored in dev->priv,
but dev->priv has never been set. Fix this.
Fixes: fc10539f7d usb: imx: Make usb-misc multi instance safe
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Make COMMON_CLK_OF_PROVIDER depend on OFTREE, this way checking for:
defined(CONFIG_OFTREE) && defined(CONFIG_COMMON_CLK_OF_PROVIDER)
can be simplified to just:
defined(CONFIG_COMMON_CLK_OF_PROVIDER)
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Port of_clk_get_parent_count() and of_clk_parent_fill() from Linux.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Pin number, as specified in OF pinumx entries, is relative to each bank
start, whereas both at91_mux_pin() and at91_pinctrl_set_conf() asssume
absolute pin numbering, so we need to take into account each bank's pin
base and convert pin number appropriately. Failing to do so results in
any pinmux configuration being applied to pins in bank A.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
if not set, barebox will use first console by default.
On this board first console is KEYBOARD_GPIO, so we will end
in unusable state.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The CPU write buffer needs to be coherent with the cache, otherwise
we might flush stale entries with the actual data stuck in the cache.
This is really important on newer CPU core with bigger write buffers.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ARMv6 K/Z derivatives have a v7 compatible MMU, but all other parts
(including the cache handling) is still at v6. As we don't make use of
the more advanced features of the v7 MMU in Barebox, it's okay to just
override this to properly identify the CPU as ARMv6.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On ARMv7 the exception vectors inside the barebox binary are used directly
by remapping the vectors base through the VBAR register. While VBAR allows
to remap the exception vectors freely, it still imposes a minimum alignment
of 32 byte, as the lower bits are treated as the exception vector offset.
Enforce this alignment inside the barebox binary.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As nand_bb_write_buf calls mtd_write(bb->mtd, cur_ofs, now, ...) the
limit that now should be checked against is bb->mtd->size - cur_ofs.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
read() might return less than $count bytes which is only an upper limit.
The user is supposed to repeat the command to fill a buffer completely.
So use the convenience wrapper read_full in memcmp.
This fixes memcmp on /dev/nand0 on an Armada XP.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
GPLv3 is incompatible with the projects license. Relicense file
under GPLv2+
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Daniel Schultz <d.schultz@phytec.de>
We have a number of sama5d3 devices that sometimes hangs at the
barebox prompt during boot due to floating RX pins. This patch
fixes the problem for us (and probably others). It is similar in
nature to linux kernel commit 138c2b2f175b ("ARM: dts: at91: fixes
dbgu pinctrl, set pullup on rx, clear pullup on tx")
While at it, remove pointless waste of power that the pullup of
the TX pins causes and fix the signal comments for SAMA5D4.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Commit 39f7a7ee8b ("i.MX: esdhc: Do not rely on CPU type for quirks")
made imx-esdhc dependent on OF and broke probing for all non-OF boards.
Since newer platforms like mx6 and vf610 are restricted to OF, the non-OF
probing only needs to distinguish mx5 vs earlier SoC.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With commit 4ed5b778a5 ("i.MX: i2c: Add Vybrid support") i2c-fsl probe
returns -EINVAL for all non-OF boards.
Since newer planforms, especially vf610 are restricted OF-only it is safe to
assume "fsl,imx21-i2c" if CONFIG_OFDEVICE is not set.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch contains the barebox implementation for the ARM
"Power State Coordination Interface" (PSCI).
The interface is aimed at the generalization of code in the following
power management scenarios:
* Core idle management.
* Dynamic addition and removal of cores, and secondary core boot.
* big.LITTLE migration.
* System shutdown and reset.
In practice, all that's currently implemented is a way to enable the
secondary core one some SoCs.
With PSCI the Kernel is either started in nonsecure or in Hypervisor
mode and PSCI is used to apply power to the secondary cores.
The start mode is passed in the global.bootm.secure_state variable. This
enum can contain "secure" (Kernel is started in secure mode, means no
PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available)
or "hyp" (Kernel is started in hyp mode, meaning it can support
virtualization).
We currently only support putting the secure monitor code into SDRAM,
which means we always steal some amount of memory from the Kernel.
To keep things simple for now we simply keep the whole barebox binary in
memory
The PSCI support has been tested on i.MX7 only so far. The only
supported operations are CPU_ON and CPU_OFF.
The PSCI and secure monitor code is based on the corresponding U-Boot
code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer
Andrey Smirnov
Oleksij Rempel
Jean-Christophe PLAGNIOL-VILLARD
Robin van der Gracht
Lucas Stach
Uwe Kleine-König
Alexander Kurz
Peter Rosin