this fix the problems introduced when detecting non ONFI flashes in
commit 4c2bdc8728
"nand_base: detect more ONFI flash"
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Thanks to the improvements brought into the kwbimage tool, it is no
longer necessary to have dummy DEST_ADDR and EXEC_ADDR lines in the
kwbimage.cfg file if those values are passed on the command line to
the kwbimage tool, which is what the Barebox build process does.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Globalscale Guruplug board is a small NAS-type plug platform that
uses a Marvell Kirkwood SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Marvell Kirkwood SoCs are based on a ARMv5 compatible core designed by
Marvell, and a large number of peripherals with Marvell Dove, Marvell
Armada 370 and Marvell Armada XP SoCs. The Marvell Kirkwood are used
in a large number of consumer-grade NAS devices, for example.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Kirkwood Marvell SoC uses a Marvell-specific implementation of an
ARMv5TE compatible ARM core, the Feroceon. This patch introduces a
Kconfig option that allows to select this CPU type.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The v0 header, used on Kirkwood, has some fields to indicate the type
of the NAND ECC, and the page size of the NAND. This commit adds
support for such fields, which are needed to support the Kirkwood
Guruplug platform.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The function image_boot_mode_id() converts the name of a boot media
into the corresponding Marvell specific code. However, 0 that we
currently used to indicate that the boot media name wasn't found,
could potentially be a valid value. So instead we use -1 to indicate a
failure.
This is also done in preparation to the introduction of
image_nand_ecc_mode_id(), which will convert a NAND ECC mode name into
the corresponding identifier. And in this case 0 is a valid identifier
of a NAND ECC mode, so we cannot use it to indicate a failure. Since
we want image_boot_mode_id() and image_nand_ecc_mode_id() to have a
consistent behavior, we change the former in this commit. The latter
is introduced in the next commit.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We now assume that at most one binary header can be added, so we no
longer need to loop for all configuration options to find the binary
blobs. We simply find the binary blob configuration option in
'binarye' and use that when we need to generate the corresponding
header.
Also, just like we did for the v0 image creation, use
image_find_option() to find the value of the different options needed
to create the main header.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Until now, the v0 image creation function was expecting the
configuration parameters to be ordered with first the configuration
parameters affecting the main header, then the DATA configuration
parameters that affect the extended header, then the payload.
However, with the recently added ability to override the destination
address or execution address, the configuration options corresponding
to those values may now appear at the end of the configuration
options. This commit allows to handle that by making the image
creation more flexible:
- The configuration options for the main header are just searched
amongst all options, the first match is used.
- When building the extension header with the DATA options, all DATA
options from the configuration file are used, in the order in which
they appear in the kwbimage.cfg file.
This will for example allow a kwbimage.cfg for a v0 image to not
specify any destination or execution address, and simply override it
from the command line.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit uses the newly introduced image_count_options() function
to:
- See if there is any DATA option that require the creation of an
extended header for v0 header.
- Verify that no more than one payload has been provided when
creating a v0 header.
- Verify that no more than one binary payload has been provided when
creating a v1 header. Technically speaking, it is possible to
support several payloads, but in real life, only one gets used, so
we will only support that to make the code simpler for now. It can
always be extended later on if needed.
- Verify that no more than one payload has been provided when
creating a v1 header.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This function returns the number of configuration elements that match
a given type. Will be used to do some sanity checking of the number of
options.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For CCMX51-boards now we do not use ESDCTL, but actual command for
adding memory is missing. This patch fix this issue.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Tegra arch will be fully based on device tree and most boards
shouldn't need anything more than the generic drivers and arch code.
This adds generic tegra20 board support, but since we currently have
no way to combine an image with a devicetree other than compiling it
into the single image we also add Colibri T20 on Iris support here
and add a defconfig for it.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There are more than Armada 370/XP in Marvell MVEBU SoC familiy. To avoid
irritation with source file nameing, we rename setup source file for
Armada 370/XP from core.c to armada-370-xp.c.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The SolidRun CuBox is a small cubic platform based on the Marvell
Dove SoC. There is nothing more than a console, yet.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit adds minimal support for the Marvell Dove SoC (88AP510) as
first SoC of the Marvell Orion family. Orion SoCs have a different timer,
therefore current mach-mvebu and Armada 370/XP Kconfig and Makefiles are
slightly modified and a new clocksource drivers is added.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When the dhcp code discovered the tftp-server-name option it immediately
tries to resolve the name. This can't succeed since the we are somewhere
in the dhcp processing and the nameserver may not even be known.
Fix this by resolving the name when dhcp is completed. While at it, do
this in a way that net_set_serverip is only called when resolv() returns
something useful. Otherwise we may end up overwriting a previously
configured serverip which came from the bootp bp_siaddr field.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Marvell Dove SoC also has an UART bootmode to upload payload after
powerup. In contrast to Kirkwood and Armada 370/XP, Dove does not
respond to a special sequence sent on UART0 but requires to be
booted into UART bootmode by bootstraps. This is usually done by
pressing a push button that will set bootstraps accordingly.
This patch adds a new option, documentation and corresponding prompts
to support the above requirements. Also a left-over option ('-p')
is removed.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds some references to Marvell Dove as it is also supported by
kwbimage.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch separates out the "generic" memory
segment registration function (of_add_memory_bank())
from of_add_memory().
The MIPS architecture has different view on memory
resources than the ARM and PPC architectures
so the "generic" of_add_memory_bank() is
unusable for the MIPS architecture.
We can add MIPS-specific of_add_memory_bank()
into arch/mips code.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds barebox.kwb and barebox.kwbuart to the list of files to
be ignored by git.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Armada XP GP platform is an evaluation platform designed by
Marvell, that uses the MV78460 quad-core SoC from the Armada XP
family.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Mirabox is a platform manufactured by Globalscale, and based on
the Marvell Armada 370 SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The OpenBlocks AX3 platform is manufactured by PlatHome and uses the
MV78260 dual-core SoC from the Armada XP family.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When a ARCH_MVEBU platform is selected, generate barebox.kwb and
barebox.kwbuart images from barebox.bin, using kwbimage.
barebox.kwb is generated by executing kwbimage on the board
kwbimage.cfg file, and is therefore designed to be booted from the
default boot media of the board, as defined by kwbimage.cfg (typically
a NAND flash or SPI flash).
barebox.kwbuart is generated by executing kwbimage on the board
kwbimage.cfg file, but by overriding the boot media to be UART. This
image is suitable for usage with the kwbtool and is generally useful
for recovery purposes.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Squashed this fixup:
arm: ensure the build doesn't fail when kwbimage lacks the binary blob
mach-mvebu images for Armada 370 and Armada XP SoC require a DDR3
training code which should be extracted from existing bootable images
for the relevant board. When such binary blob has not been extracted,
the build of the .kwb and .kwbuart images will fail. This is annoying
as it makes the build of all Armada 370/XP defconfig fail, which can
be a problem for automated builds.
This proposal makes the failure of kwbimage not a fatal failure for
the build process, and shows a warning. The user therefore sees:
====================================================================
KWB barebox.kwb
Didn't find the file 'plathome-openblocks-ax3-binary.0' in '/home/thomas/projets/barebox' which is mandatory to generate the image
This file generally contains the DDR3 training code, and should be extracted from an existing bootable
image for your board. See 'kwbimage -x' to extract it from an existing image.
Could not create image
WARNING: Couldn't create KWB image due to previous errors.
KWBUART barebox.kwbuart
Didn't find the file 'plathome-openblocks-ax3-binary.0' in '/home/thomas/projets/barebox' which is mandatory to generate the image
This file generally contains the DDR3 training code, and should be extracted from an existing bootable
image for your board. See 'kwbimage -x' to extract it from an existing image.
Could not create image
WARNING Couldn't create KWB image due to previous errors.
====================================================================
The only drawback is that barebox-flash-image, which normally points
to barebox.kwb, becomes a stale symbolic link.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit adds minimal support for the Armada 370 and Armada XP SoCs
from Marvell.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Without this patch after compiling barebox
for a PowerPC board we have 'git status'
output looking like this:
# Untracked files:
# (use "git add <file>..." to include in what will be committed)
#
# arch/ppc/boards/pcm030/barebox.lds
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
See also:
commit eb84709192
Author: Sascha Hauer <s.hauer@pengutronix.de>
Date: Mon Mar 25 15:18:38 2013 +0100
clk: remove unused __clk_[get|put]
This is some unused code resulting from copying stuff from
the kernel. Remove it.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a pinctrl driver for the Tegra 20 line of SoCs. It only
supports the three basic pinconfiguration settings function mux,
tristate control and pullup/down control.
The driver understands the same devicetree bindings as the Linux one,
unimplemented pinconfiguration options will be ignored.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This tool is used with Marvell EBU SoC to trigger the UART boot mode
provided by the SoC BootROM, and push the bootloader image to the
target using the Xmodem protocol.
It has been taken from the U-Boot source code, with minor
modifications to make it work with Armada 370/XP platforms.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Marvell EBU SoCs (Kirkwood, Armada 370, Armada XP) have a BootROM
that understand a specific image format, composed of a main header,
several extension headers and a paylod. This image can be booted from
NAND, SPI, SATA, UART, NOR, etc.
This patch adds a tool that allows to extract the components and
configuration of existing images, and to create new images.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The missing 'break' statement lets look an i.MX23 like an i.MX28.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Using the MXS MCI driver with an eight bit capable eMMC results into the
'devinfo' message the interface uses '0' bits for data transfer:
barebox:/ devinfo mxs_mci0
resources:
num : 0
start : 0x80034000
size : 0x00002000
driver: mxs_mci
bus: platform
Interface
Min. bus clock: 1476 Hz
Max. bus clock: 48000000 Hz
Current bus clock: 24000000 Hz
Bus width: 0 bit
The eight bit interface width is stored internally as value '2'. And a two bit
'2' ends up into 0xfffffffe when used as an array index. Using an unsigned
field instead fixes this issue:
barebox:/ devinfo mxs_mci0
resources:
num : 0
start : 0x80034000
size : 0x00002000
driver: mxs_mci
bus: platform
Interface
Min. bus clock: 1476 Hz
Max. bus clock: 48000000 Hz
Current bus clock: 24000000 Hz
Bus width: 8 bit
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Ingenic JZ4740, JZ4755 and JZ4770 SoCs use
the same IP core for UART interface. This IP core
is NS16550-compatible, but it needs small workaround.
This commit moves the UART code for Ingenic SoCs
from board level to machine level. So the code
can be reused for different boards or even
different SoCs.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This partly reverts:
commit 697e02b74f
Author: Alexander Shiyan <shc_work@mail.ru>
Date: Tue Jan 22 15:08:31 2013 +0400
ARM: ccmx51: Remove SDRAM size settings
This patch removes SDRAM memory size setting from board due
to auto detect last one by ESDCTL.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The board originally configured the SDRAM controller for the
maximum size and detected the usable SDRAM size by reading the
board id. This became broken after switching to automatic SDRAM
size detection by reading back ESDCTL values.
This patch brings back the old behaviour.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some boards setup more memory than they actually have. The real memory
size can then be detected later for example by reading a board id.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In commit ad09b59f8b "ARM i.MX31: give
register base addresses a proper MX31_ prefix", the IOMUX GPR setup
to enable USBH2 was replaced with an incorrect source register.
Instead of reading the GPR register, USBOTG HWHOST is used as rmw source,
which contains 0x10020001.
Beside the intended GPR[11] setup ("Enable USBH2 signals on AudioPort 3 and
AudioPort6"), this erroneously also sets
GPR[28] enable USBOTG loopback
GPR[17] override DSR_DCE1 with USBOTG_DATA4
GPR[0] select FIR DMA requests instead of UART2 DMA
Beside breaking UART2, it probably also broke some UART1 and USB OTG setups.
Fix this and replace the address with the appropriate defines.
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The prefix/cleanup series
ad09b59f8ba8c63596674c53af062b
missed a few unprefixed IOMUXC_BASE define users. Fix these.
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Eric Bénard
Sascha Hauer
Thomas Petazzoni
Alexander Shiyan
Lucas Stach
Sebastian Hesselbarth
Antony Pavlov
Juergen Beisert
Alexandre Belloni
Jean-Christophe PLAGNIOL-VILLARD
Andreas Pretzsch