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15323 Commits

Author SHA1 Message Date
Andrey Smirnov 56f3bd1cd3 usb: ohci-at91: Check result of clk_get()
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-03-09 11:51:27 +01:00
Andrey Smirnov 6dc7545135 serial: atmel: Check result of clk_get()
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-03-09 11:51:27 +01:00
Andrey Smirnov 3494084017 of: base: Use scoring in DT device matching
Port Linux kernel algorithm for both of_device_is_compatible() and
of_match_node(). With this change former now returns a score on the
scale of 0 to INT_MAX/2, and the latter goes through all compatiblity
entries and selects the entry that has the best matching score.

This is needed for SoCs where IP blocks are backwards compatible and
corresponding OF nodes can proclaim compatibility with several entries
found in driver's compatiblity table. One such example would be PIO
pinctrl block on AT91SAM9x5 SoCs which declare compatibility with with
both "atmel,at91sam9x5-pinctrl" and "atmel,at91rm9200-pinctrl".

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-03-09 11:51:27 +01:00
Andrey Smirnov a8b41f2c72 clk: Make COMMON_CLK_OF_PROVIDER depend on OFTREE
Make COMMON_CLK_OF_PROVIDER depend on OFTREE, this way checking for:

	defined(CONFIG_OFTREE) && defined(CONFIG_COMMON_CLK_OF_PROVIDER)

can be simplified to just:

	defined(CONFIG_COMMON_CLK_OF_PROVIDER)

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-03-09 08:13:38 +01:00
Andrey Smirnov b5ea2c6acc clk: Port two helper functions from Linux
Port of_clk_get_parent_count() and of_clk_parent_fill() from Linux.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-03-09 08:13:38 +01:00
Andrey Smirnov da1752b370 pinctrl: at91: Implement .get_direction hook
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-03-09 08:13:38 +01:00
Andrey Smirnov 15426d5c46 pinctrl: at91: Fix a bug in at91_pinctrl_set_state()
Pin number, as specified in OF pinumx entries, is relative to each bank
start, whereas both at91_mux_pin() and at91_pinctrl_set_conf() asssume
absolute pin numbering, so we need to take into account each bank's pin
base and convert pin number appropriately. Failing to do so results in
any pinmux configuration being applied to pins in bank A.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-03-09 08:13:38 +01:00
Andrey Smirnov 7d9679a33a pinctrl: at91: Fix a bug in at91_pinctrl_set_conf()
Pin_to_controller returns struct at91_gpio_chip, whereas at91_mux_*
functions expect void __iomem * pointing to controller register
window. Fix the code to do appropriate conversion between the two.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-03-09 08:13:38 +01:00
Andrey Smirnov 943a9eeac4 regmap: Implement syscon_node_to_regmap()
Implement syscon_node_to_regmap() to simplify porting kernel code.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-03-09 08:13:38 +01:00
Andrey Smirnov 2574148ad9 at91: Fix bug/typo in debug_ll.h
Correct "COFNIG" to "CONFIG".

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-03-09 08:13:38 +01:00
Peter Rosin 31e16d1769 at91: serial: pullup RX pins, do not pullup TX pins
We have a number of sama5d3 devices that sometimes hangs at the
barebox prompt during boot due to floating RX pins. This patch
fixes the problem for us (and probably others). It is similar in
nature to linux kernel commit 138c2b2f175b ("ARM: dts: at91: fixes
dbgu pinctrl, set pullup on rx, clear pullup on tx")

While at it, remove pointless waste of power that the pullup of
the TX pins causes and fix the signal comments for SAMA5D4.

Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-14 08:54:59 +01:00
Alexander Kurz b225bbf295 i.MX: esdhc: fix imx-esdhc driver for non-OF boards
Commit 39f7a7ee8b ("i.MX: esdhc: Do not rely on CPU type for quirks")
made imx-esdhc dependent on OF and broke probing for all non-OF boards.
Since newer platforms like mx6 and vf610 are restricted to OF, the non-OF
probing only needs to distinguish mx5 vs earlier SoC.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-14 08:48:34 +01:00
Alexander Kurz 45164aadfa i.MX: i2c: fix i2c-fsl for non-OF boards
With commit 4ed5b778a5 ("i.MX: i2c: Add Vybrid support") i2c-fsl probe
returns -EINVAL for all non-OF boards.
Since newer planforms, especially vf610 are restricted OF-only it is safe to
assume "fsl,imx21-i2c" if CONFIG_OFDEVICE is not set.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-14 08:48:25 +01:00
Sascha Hauer 4afb09cc67 Merge branch 'for-next/net' 2017-02-13 09:26:04 +01:00
Sascha Hauer 5a30fae8c7 Merge branch 'for-next/mvebu' 2017-02-13 09:26:04 +01:00
Sascha Hauer 2cd2bad2b7 Merge branch 'for-next/misc' 2017-02-13 09:26:04 +01:00
Sascha Hauer 30139163b7 Merge branch 'for-next/imx' 2017-02-13 09:26:04 +01:00
Sascha Hauer bb1a6a2fd3 Merge branch 'for-next/efi' 2017-02-13 09:26:04 +01:00
Sascha Hauer a06513273f Merge branch 'for-next/dts' 2017-02-13 09:26:03 +01:00
Sascha Hauer a9ba8a1d0d Merge branch 'for-next/arm' 2017-02-13 09:26:03 +01:00
Sascha Hauer 19df384cec ARM: i.MX7: Add PSCI support
This adds the SoC specific PSCI bits for i.MX7. Based on the
corresponding U-Boot code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-13 08:35:42 +01:00
Sascha Hauer cc407b4113 ARM: Add PSCI support
This patch contains the barebox implementation for the ARM
"Power State Coordination Interface" (PSCI).

The interface is aimed at the generalization of code in the following
power management scenarios:
* Core idle management.
* Dynamic addition and removal of cores, and secondary core boot.
* big.LITTLE migration.
* System shutdown and reset.

In practice, all that's currently implemented is a way to enable the
secondary core one some SoCs.

With PSCI the Kernel is either started in nonsecure or in Hypervisor
mode and PSCI is used to apply power to the secondary cores.

The start mode is passed in the global.bootm.secure_state variable. This
enum can contain "secure" (Kernel is started in secure mode, means no
PSCI), "nonsecure" (Kernel is started in nonsecure mode, PSCI available)
or "hyp" (Kernel is started in hyp mode, meaning it can support
virtualization).

We currently only support putting the secure monitor code into SDRAM,
which means we always steal some amount of memory from the Kernel.
To keep things simple for now we simply keep the whole barebox binary in
memory

The PSCI support has been tested on i.MX7 only so far. The only
supported operations are CPU_ON and CPU_OFF.

The PSCI and secure monitor code is based on the corresponding U-Boot
code.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-13 08:35:42 +01:00
Wadim Egorov 436fb44220 config: Set UART port 2 as debug port
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-10 13:19:40 +01:00
Wadim Egorov 49b321fb89 serial: ns16550: Set read/write functions depending on reg-io-width
Set proper register read/write functions depending on reg-io-width
device tree property.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-10 13:19:40 +01:00
Wadim Egorov 14c6fc99e1 ARM: phycore-rk3288: Use UART2 as debug output
RK3288's UART2 is the default debug uart interface.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-10 13:19:40 +01:00
Sascha Hauer cbf19c96ef dts: update to v4.10-rc6
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-10 08:51:35 +01:00
Sascha Hauer f4db58d47c dts: update to v4.10-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-10 08:51:32 +01:00
Sascha Hauer 17c6b31c41 dts: update to v4.10-rc4
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-10 08:51:26 +01:00
Sascha Hauer d01aad9b1c Release v2017.02.0
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-10 08:49:58 +01:00
Sascha Hauer 857f69ba8c ARM: start: Fix image size calculation
In barebox_non_pbl_start() we do not run at the address we are linked
at, so we must read linker variables using ld_var(). Since ld_var()
current is not available on arm64 we create two zero sized arrays,
one at the begin of the image and one at the end. The difference
between both is the image size we are looking for.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-08 12:03:20 +01:00
Sascha Hauer cdf33e6ecf ARM: Add smc call support
Taken from the Kernel: A wrapper to make a smc call from C.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-08 09:18:57 +01:00
Sascha Hauer b94205dc97 ARM: Add UNWIND macro
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-08 09:18:53 +01:00
Andrey Smirnov aefc67826e i.MX: vf610: Add support for ZII VF610 Dev Family
Add support for ZII VF610 Dev based designs such as:

    - VF610 Dev, revision B
    - VF610 Dev, revision C
    - CFU1, revision A
    - SPU3, revision A
    - SCU4 AIB, revision C

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-07 09:46:38 +01:00
Sascha Hauer 1dfe9f050f ARM: i.MX7: Initialize CSU
The CSU needs to be initialized, otherwise we cannot access memory
in non secure mode.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 16:13:10 +01:00
Sascha Hauer 55eed47d85 ARM: i.MX7: Add imx7s.dtsi
Needed for compiling the i.MX7 warp board which already includes this
file.

This file is necessary because the upstream dtsi file currently assigns
MX7D_CLK_DUMMY to the gpt1 clock we use, so we won't get a meaningful
clock rate.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 11:54:50 +01:00
Sascha Hauer ad200f0dc3 pinctrl: i.MX7: Fix LPSR sel_imput setting
The i.MX7 has two pinmux controllers, the regular and the LPSR
controller. The LPSR pinmux controller doesn't have any sel_input
registers, instead they can be found in the regular pinmux controller.
This means whenever we want to apply the the sel_input setting for
the LPSR controller, we have to apply them to the regular controller
instead.
In barebox take the easy way out and just add the difference of the
two base addresses to the register offset. The same issue is present
in the Kernel aswell, but when the bootloader already configured
the pins correctly nobody notices when the Kernel sel_input setup
effectively is a no-op.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 11:51:20 +01:00
Sascha Hauer f7165017f4 ARM: start: Fix boarddata allocation
It's essential that we always pass the same size value to
arm_mem_barebox_image(), otherwise the result will be inconsistent.
Pass arm_barebox_size instead of barebox_image_size as the latter
does not contain the max bss segment size.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 11:49:03 +01:00
Sascha Hauer c82e1f90d2 clk: i.MX7: setup ethernet clocks
Reparent ethernet clocks so that they can be used by the
fec driver. The values are the same as U-Boot uses.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 07:41:56 +01:00
Sascha Hauer 75cb02078e clk: i.MX7: do not register PLL bypass clocks as separate clocks
In the Kernel the bypass bits in the PLLs are now registered as
separate clocks and are no longer handled in the PLL code. In
barebox we haven't made this step and there currently seems to
be no reason to do so.
This means that the bypass bits are currently modified in both
the PLL driver and in the separate clocks which does not work
properly. Drop all the bypass clocks to let the bypass bits
be handled in the PLL driver exclusively.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 07:41:10 +01:00
Sascha Hauer 23aa31a6d2 clk: i.MX7: Fix ethernet clocks
The original clock code from Linux registers some gates at
base + 0x44e0, 0x44f0, 0x4500, 0x4510. These are not in the reference
manual and do not seem to have any effect on the hardware. The
reference manual lists clocks at 0x4700 and 0x4710 which Linux
does not control at all. These clocks really do have an effect on
the hardware and are needed for ethernet support. Register the
existing clocks rather than the made up clocks to support
ethernet.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 07:40:23 +01:00
Sascha Hauer 2225c194ed clk: Add support for shared gates
Sometimes a single software control knob controls multiple gates
in hardware. This patch adds support for shared gates which help
coping this situation. The first gate is registered with the hardware
gate as usual, the others are registered as shared gates which does
not have hardware control itself, but only switches the real hardware
gate.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 07:34:03 +01:00
Sascha Hauer bce7942877 clk: i.MX7: do clock reparenting when all clocks are initialized
By the time the i.MX7 clock driver probes the fixed clocks which
are the roots of the clock tree are not yet present, so reparenting
especially to one of the fixed clocks does not work. Move the
tree setup to a later initcall when the fixed clocks are there.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 07:32:22 +01:00
Sascha Hauer f5409645e9 clk: i.MX: Pass CLK_OPS_PARENT_ENABLE where necessary
CLK_OPS_PARENT_ENABLE was missing on some i.MX7 specific clocks.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 07:31:48 +01:00
Sascha Hauer f573cd5e40 clk: i.MX: clk-gate2: Allow to pass flags
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 07:31:25 +01:00
Sascha Hauer bea07a6881 clk: implement CLK_OPS_PARENT_ENABLE
Some clocks may only be modified when their parent clocks are enabled.
The kernel has the CLK_OPS_PARENT_ENABLE flag for this purpose.
Implement it for barebox aswell.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 07:31:12 +01:00
Sascha Hauer c21794d0ee clk: Keep enable count consistent over reparent
When reparenting a clock we have to make sure the new parent is enabled
when the clock was enabled on the old parent. Also we have to decrease
the old parents use counter when the clock was enabled.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-06 07:31:00 +01:00
Alexander Kurz 4cb70c729f ARM i.MX: Add i.MX6SL support
Most i.MX6SL infrastructure is already covered in barebox by general i.MX6
support. Missing infrastructure provided in separate commits are
* SoC type detection
* Clock infrastructure

Add the missing fsl,imx6sl-mmdc, so it will not be catched by fsl,imx6q-mmdc
and the remaining bits and pieces to provide barebox i.MX6SL SoC support.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-02 08:13:07 +01:00
Alexander Kurz cb3a2b7be8 ARM: i.MX6SL: import clock infrastructure from linux
Import i.MX6SL clock infrastructure from linux clk-imx6sl.c

To save space, clocks beeing unlikely usefull for bootloader purposes
(SSI, SPDIF, EXTERN_AUDIO) were not imported.
Further, the fixup code from linux mainline commits
a49e6c4b8204 ("ARM: imx: add common clock support for fixup mux")
cbe7fc8aaeef ("ARM: imx: add common clock support for fixup div")
was ignored for this commit.

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-02 08:13:07 +01:00
Alexander Kurz 9a16b02642 ARM i.MX: add SoC type detection for i.MX6SL
The i.MX6 series SoC type is determined by barebox by examining the
USB_ANALOG_DIGPROG aka IMX6_ANATOP_SI_REV register. This register is located
at a common offset for all mx6 SoC - except for i.MX6SL where a different
offset is used. This creates a dilemma while distinguishing the mx6sl from
non-mx6sl SOC since the SoC type identification register location is type
specific itself.

Access to undocumented and probably invalid or unpredictable registers should
be avoided as possible. For the mx6sl detection an access to the general
USB_ANALOG_DIGPROG @0x260 cannot be avoided when running on mx6sl. This
register contained the value 0x00014009 for different mx6sl Rev. 1.2 based
e-book readers using MCIMX6L7DVN10AB and MCIMX6L8DVN10AB SoC. This
implementation assumes the value of MAJOR_UPPER (here 0x01) to be smaller
than the smallest non-6sl MAJOR_UPPER (0x61 for mx6s).

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-01 08:44:36 +01:00
Alexander Kurz 3c95ce10a4 ARM i.MX: move cpu_type macros in front of cpu_revision code
Preparational commit to enable the use of cpu_type macros in imx6_cpu_revision()

Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2017-02-01 08:44:36 +01:00