Currently only second stage booting from the vendor U-Boot is tested. I
don't want to flash barebox into NAND yet because UART-booting for
recovery doesn't work for me.
Working so far are:
- UART
- networking
- nand flash
Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This replaces the reset_cpu() function which every SoC or board must
provide with registered handlers. This makes it possible to have multiple
reset functions for boards which have multiple ways to reset the machine.
Also boards which have no way at all to reset the machine no longer
have to provide a dummy reset_cpu() function.
The problem this solves is that some machines have external PMICs or
similar to reset the system which have to be preferred over the
internal SoC reset, because the PMIC can reset not only the SoC but also
the external devices.
To pick the right way to reset a machine each handler has a priority. The
default priority is 100 and all currently existing restart handlers are
registered with this priority. of_get_restart_priority() allows to retrieve
the priority from the device tree which makes it possible for boards to
give certain restart handlers a higher priority in order to use this one
instead of the default one.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for Marvell Armada XP based 4-bay NAS Lenovo
Iomega ix4-300d.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Before adding new Armada XP based boards becomes messier than necessary,
sort Armada XP based board Kconfig and image Makefile alphabetically.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With proper defines for ARMADA_370_XP_FABRIC_CTRL and MBUS_ERR_PROP_EN
make use of it.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Commit 6638760c22
("ARM: mvebu: Enable PUP register")
correctly enables devices that are disabled after boot-up due to
some Design For Testability registers.
However, although harmless on Armada 370, call the code conditionally
on Armada XP only. While at it, move PUP register defines to SYSCTL
registers where they belong to.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Marvell Armada XP MV78230-A0 incorrectly identifies itself as MV78460.
Check number of CPUs in FABRIC_CONF and fixup PCIe DEV_ID when it is
2 CPUs instead of 4.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To prepare PCIe device id fixups, move PCIe register defines
to a common location.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Registering mbus driver as platform driver is a little late for
some register accesses to work. We have to make sure boot-up
mbus windows are disabled early, so call mbus driver directly
from SoC init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This file originates in Linux. Linux has it under include/linux/
directory since commit dccd2304cc90.
Let's move it to the same place as well in barebox.
This commit was generated by the following commands:
find -name '*.[chS]' | xargs sed -i -e 's:<sizes.h>:<linux/sizes.h>:'
git mv include/sizes.h include/linux/
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As reported by Sebastian, we need to enable this explicitly for the
Tx clock on RGMII. While here, let's enable all the other peripherals.
Although this is documented to be required only for Armada XP SoC,
it has been found to be harmless on Armada 370, so we do it unconditionally
to simplify the code.
Reported-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now that the correct SoC specific memory fixup function is called
we can allow to select multiple SoCs in Kconfig.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Only run the fixup when we are actually on the corresponding
SoC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The initialisation of the memory nodes on mvebu is a bit
compilcated:
pure_initcall(mvebu_memory_fixup_register)
of_register_fixup(mvebu_memory_of_fixup, NULL)
core_initcall(kirkwood_init_soc)
mvebu_set_memory()
core_initcall(of_arm_init)
of_fix_tree()
mvebu_memory_of_fixup()
First a mvebu common of_fixup function is registered, then the SoC
calls mvebu_set_memory which stores the memory base and size in global
variables. Afterwards the of_fixup is executed which fixes the memory
nodes according to the global variables.
Instead register a SoC specific fixup which directly calls mvebu_set_memory
with the memory base and size as arguments:
pure_initcall(kirkwood_register_soc_fixup);
of_register_fixup(kirkwood_init_soc, NULL);
core_initcall(of_arm_init)
of_fix_tree()
kirkwood_init_soc()
mvebu_set_memory(phys_base, phys_size);
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Multi-SoC support for MVEBU will add mbus ranges for all compiled
SoCs. To protect the mbus node of the SoC barebox is executed on
from others ranges, pass machine's compatible to mvebu_mbus_add_range
and check before applying the fixup.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
mvebu has a reset_cpu function per SoC this does not work when multiple
SoCs are selected, so add a common reset_cpu function which calls into
the SoC specific ones.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- Remove OFDEVICE dependency from PINCTRL. It won't do
much then, so add a comment to Kconfig when PINCTRL is
selected without OFDEVICE
- Let Architectures only select PINCTRL instead of the
particular driver. Change the drivers to 'default y if $SOC'
to make sure the drivers are still compiled if the corresponding
SoC is selected
This fixes Kconfig warnings like:
warning: (PINCTRL_ARMADA_370 && PINCTRL_ARMADA_XP && PINCTRL_DOVE && PINCTRL_KIRKWOOD) selects PINCTRL which has unmet direct dependencies (OFDEVICE)
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This commit adds a new Marvell Kirkwood-based board, by following the currently
supported boards.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On Marvell MVEBU SoCs memory size is set up by BootROM and can be read
from SoC's RAM controller. With early DT fixups available, set corresponding
DT node to reflect accessible amount of directly attached RAM.
This patch also removes non-DT call to arm_add_mem_device to silence a
warning about request_region conflict due to adding a mem device twice.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For each supported MVEBU SoC, add the corresponding remapped registers
to fix them up in provided DTBs.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a pinctrl driver for pin muxing on Marvell Armada XP. The
driver is ported from Linux and modified to fit on Barebox's common
mvebu pinctrl driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a pinctrl driver for pin muxing on Marvell Armada 370. The
driver is ported from Linux and modified to fit on Barebox's common
mvebu pinctrl driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds pinctrl drivers for Marvell Dove and Kirkwood SoCs based
on a common driver stub. This design is based on the corresponding
Linux driver and should ease additional drivers for Marvell Armada
SoCs.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Marvell MVEBU SoC id and revision can be read out from any PCIe port
registers. This adds corresponding code to read out id and revision
and provides a helper function for drivers to use it.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With all SoCs converted to DT based probing, select
PBL_MULTI_IMAGES support and get rid of SoCs Kconfig
choice to allow multiple boards to be selected.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
With Armada 370/XP DT files available, convert Armada 370/XP SoC init
to register basic devices from DT only. Makefile targets for dtbs will
be removed again as soon as MULTI_PBL is available.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
With Kirkwood DT files available, convert Kirkwood SoC init
to register basic devices from DT only. Makefile targets for
dtbs will be removed again as soon as MULTI_PBL is available.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Armada XP timers can be run from a 25MHz fixed clock. Add the corrsponding
clock and clock alias to SoC setup.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
mach-mvebu has two files containing lowlevel code. Consolidate both into
mach-mvebu/lowlevel.c. Also put the now empty mach-mvebu/common.c into
non-lowlevel obj-y as it will be used for common non-lowlevel code later.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
All current boards use the same TEXT_BASE, therefore set the default
TEXT_BASE by SoC instead of by board.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Mostly to make it clear that boarddata needs to be
something we can dereference.
As this is a pretty invasive change, use the opportunity
to make the signature 64bit safe.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current implementation fakes a memory-mapped I/O device
at 0x3f8 and 0x2f8, then uses platform read/write functions
to do the actual reading and writing. These platform functions
only exist for the x86 platform; better to move the I/O
routines into the driver and have the driver request I/O ports
using request_ioport_region.
Signed-off-by: Michel Stam <michel@reverze.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
gpiolib user have nothing to define in their machine
specific gpio.h, so do not include it.
The only thing they could define would be ARCH_NR_GPIOS,
but currently no architecture defines it. Should an architecure
feel the need to do it this would be a good opportunity to
get rid of this limitation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With OF clock providers, we can now remove temporary clocks and clock
aliases. Also, non-DT device probing for timer and serial is removed.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With multiboard support the compiletime generated BOARDINFO string
gets more and more meaningless. This removes it from Kconfig and
replaces it with a variable that can be set at boardlevel.
Also many boards have a standard setting for the hostname in the
environment. This patch also moves the standard to C code by calling
barebox_set_hostname().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch provides a global cleanup barebox Kconfig files. This includes
replacing spaces to tabs, formatting in accordance format.
No functional changes.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Successfully boots to console via kwboot. No other functionality yet.
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds clock aliases for spi controllers found on Dove to allow
spi driver to get tclk frequency.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a DT only driver for the GPIO controller found on Marvell
Orion/MVEBU SoCs (Armada 370/XP, Dove, Kirkwood, MV78x00, Orion5x).
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This converts Armada 370/XP SoC init to register tclk alias
for timer by physbase instead of name.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This converts Kirkwood and Dove SoC init to register tclk alias
for timer by physbase instead of name.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Clocks need to be accessed early for DT support, so move soc_init to
core_initcall instead of postcore_initcall.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
At early stage after boot, all MVEBU SoCs are similar enough to have
a common lowlevel and barebox entry. We also remap the internal register
base address to 0xf100000 as it gives some 512M more of contiguous address
space. As we cannot determine real memory size that early, we start with
a default memory size of 64M and probe correct size later in SoC init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Uwe Kleine-König
Sascha Hauer
Sebastian Hesselbarth
Masahiro Yamada
Ezequiel Garcia
Lucas Stach
Michel Stam
Alexander Shiyan
Jason Cooper