Kernel does not have pinctrl driver for i.MX27 yet. When we using DT,
this cause to unable setup pins to desired function. This patch adds
a setup for MC13783 IRQ pin to avoid this issue.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This settings taken from original DIGI U-boot source code.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Without this patch the chipidea driver reports 'No supported role'
during runtime.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Patch will help to develop user devices connected to module, so
user can operate GPIOs in barebox console.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In omap4_enable_all_clocks we not only enable the mcbsp clocks, but also
change the source from ABE_24M_FCLK to 24M_FCLK. Revert this and default
to the reset state.
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch fixes boot_mode detection for non-internal boot and
bootsource detection for i2c boot. Further, the bootsouce_instance
is now determined for spi, i2c, and mmc/sd boot.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is mainly a backport of the imx6_revision function of
arch/arm/mach-imx/mach-imx6q.c in the linux kernel sources.
Signed-off-by: S. Fricke <sfricke@data-modul.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Use MMC_CAP_ names instead of MMC_MODE_. This makes it more
clear that these are capabilities of host/card and do not refer
to the current mode. These are in line with the Linux Kernel
except for MMC_CAP_MMC_HIGHSPEED_52MHZ which could be fixed
later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
After Reset VMMC goes to default VSEL. This is not a clean power cycle for
some SD cards.
Set flag WR_S for VMMC to avoid going to default VSEL.
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds several missing includes to files under include/ which
we relied on being included implicitly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Without devicetree support we print the Kernel commandline in
verbose mode. Do the same with devicetree boot aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
when doing bootm -v -v we dumped the original tree to the console.
Make sure to print the fixed tree instead so that the fixups can
be examined.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds host tools for i.MX to generate the i.MX internal
flash header format and a tool to upload these images to an
i.MX SoC via USB.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is a port of the official PLL errata workaround from Freescale.
The PLL's in the i.MX51 processor can go out of lock due to a metastable
condition in an analog flip-flop when used at high frequencies.
This workaround implements an undocumented feature in the PLL (dither
mode), which causes the effect of this failure to be much lower (in terms
of frequency deviation), avoiding system failure, or at least decreasing
the likelihood of system failure.
This is based on U-Boot commit:
commit 9db1bfa110ac411ab3468e817f7f74b2439eb8c8
Author: David Jander <david@protonic.nl>
Date: Wed Jul 13 21:11:53 2011 +0000
ARM: MX51: PLL errata workaround
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This chipselect is used on RDK Zigbee connector. Since we cannot
define additional chipselect after SPI is initialized, define this one
in main SPI initialization in PCM038 SOM.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We always must decend into the pbl build. Otherwise it doesn't get
rebuilt if only sourcefiles from the pbl are changed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add config to select RAM assembly. The difference is if one or two chip selects
are used. This can't be checkt at runtime.
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The default baseboard for the tqma53 (MBa53) uses UART2 for debug console.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On ARM the boarddirs are only cleaned due to the regular file
pattern search, but are not explicitly cleaned. This makes
it impossible to clean files which are not matched by a pattern
but have to be explicitly cleaned due to adding them to extra-y.
This patch changes the board-/board-y variables to += so that
we can use $(board-) to add it to common-. This way the board
directories are also cleaned.
While touching the board-y variables anyway order them
alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a command to generate the zynq image instead of generating it
directly. This causes a rebuild exactly when necessary and prints
a "ZYNQ-IMG" to the commandline during compilation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The pbl used 'zbarebox.bin' as target instead of the real file. This
lead to strange effects that the images depending on zbarebox.bin were
only built every second time. This uses the full path as target.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As new breakout boards are being developped, we need to add their IDs in
the device detection code, otherwise they will be treated as regular
CFA-10036.
Signed-off-by: Brian Lilly <brian@crystalfontz.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This switches the babbage board to probe from devicetree for all
for all devices we currently support probing from devicetree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The mc13892 driver knows that it needs spi-cs-high, so the mc13892
will work. The dataflash also connected to this bus though can only
be probed when the mc13892 is inactive. Due to driver probe differences
we can only make sure the mc13892 is inactive when we put the information
into the devicetree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The boot source for the i.MX23 is configured via a few GPIOs, which are later
be used for different purposes (like LCD data for example). The SoC internal
ROM reads these GPIOs and uses the selected boot source.
For various reasons the boot source is also of interest when Barebox is running.
This detection approach reads again the GPIOs. It switches temporarily the pins
to act as GPIOs and input, reads their settings, and switches back to their
previous functions.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some SoCs come up with invalid entries in the data cache. This can
lead to memory corruption when we enable them later, so invalidate
the caches early.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Lucas Stach <l.stach@pengutronix.de>
At least the iMX6 boot rom seems to jump into barebox with a non
invalidated d-cache which causes data corruption when
v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides
stack or other valid data.
That's why the cache must be invalided for this processors explicitly
(e.g. in barebox_arm_reset_vector()). Operation differs from flush only
in one instruction so that patch modifies the existing
v7_mmu_cache_flush() function slightly by adding an optional argument.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Registers 'r0' till 'r3' are scratch registers and do not need to be
restored.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On ARMv7 the intention is to disable the alignment trap to be able to
use hardware assisted unaligned load/stores. Fix the init to do the
right thing.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Kernel dts relies on reset default pad settings for the FEC.
Add correct pad settings.
Also, add missing MX51_PAD_NANDF_D11__FEC_RX_DV.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
From Kernel commit 418df63a ARM: 7670/1: fix the memset fix
| Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
| recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
| with the memset return value. However the memset itself became broken
| by that patch for misaligned pointers.
|
| This fixes the above by branching over the entry code from the
| misaligned fixup code to avoid reloading the original pointer.
|
| Also, because the function entry alignment is wrong in the Thumb mode
| compilation, that fixup code is moved to the end.
|
| While at it, the entry instructions are slightly reworked to help dual
| issue pipelines.
|
| Signed-off-by: Nicolas Pitre <nico@linaro.org>
| Tested-by: Alexander Holler <holler@ahsoftware.de>
| Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
At early stage after boot, all MVEBU SoCs are similar enough to have
a common lowlevel and barebox entry. We also remap the internal register
base address to 0xf100000 as it gives some 512M more of contiguous address
space. As we cannot determine real memory size that early, we start with
a default memory size of 64M and probe correct size later in SoC init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This just add more visible separators between each subconfig of the
supported Marvell EBU SoCs.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When using a builtin dtb the builtin dtb is built twice, once
from as a dependency of the 'dtbs' target and once as a dependency
of the corresponding dtb.o target. This can happen in parallel
with parallel make which results in build corruption when two
processes try to generate the dtb at the same time. Typical errors
include:
fixdep: error opening depfile: arch/arm/dts/.imx51-babbage.dtb.d: No such file or directory
make[1]: *** [arch/arm/dts/imx51-babbage.dtb] Error 2
fixdep: arch/arm/dts/.imx51-babbage.dtb.d is empty
mv: cannot stat `arch/arm/dts/.imx51-babbage.dtb.tmp': No such file or directory
make[1]: *** [arch/arm/dts/imx51-babbage.dtb] Error 1
To fix this build the devicetree blobs using extra-y instead of
a separate target.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Although conclusions in 50d1b2de8e "ARM
v7: Fix register corruption in v7_mmu_cache_off" are correct, the
implemented fix is not complete because the following failure can
happen:
1. d-cache contains the cache line around 'sp'
2. v7_mmu_cache_off() disables cache
3. early v7_mmu_cache_flush() pushes 'lr' on uncached stack
4. v7_mmu_cache_flush() flushes d-cache and can override stack written
by step 3.
5. v7_mmu_cache_flush() pops 'lr' out of cache and jumps to it which
might be random data now.
Patch avoids step 3 which is easy because 'lr' is never modified by the
function. By using the 'r12' scratch register instead of 'r10', the
whole initial 'push' can be avoided.
Patch moves also the 'DMB' operation so that it is executed after data
has been pushed on stack.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Thanks to the improvements brought into the kwbimage tool, it is no
longer necessary to have dummy DEST_ADDR and EXEC_ADDR lines in the
kwbimage.cfg file if those values are passed on the command line to
the kwbimage tool, which is what the Barebox build process does.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Globalscale Guruplug board is a small NAS-type plug platform that
uses a Marvell Kirkwood SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Marvell Kirkwood SoCs are based on a ARMv5 compatible core designed by
Marvell, and a large number of peripherals with Marvell Dove, Marvell
Armada 370 and Marvell Armada XP SoCs. The Marvell Kirkwood are used
in a large number of consumer-grade NAS devices, for example.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Kirkwood Marvell SoC uses a Marvell-specific implementation of an
ARMv5TE compatible ARM core, the Feroceon. This patch introduces a
Kconfig option that allows to select this CPU type.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For CCMX51-boards now we do not use ESDCTL, but actual command for
adding memory is missing. This patch fix this issue.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Tegra arch will be fully based on device tree and most boards
shouldn't need anything more than the generic drivers and arch code.
This adds generic tegra20 board support, but since we currently have
no way to combine an image with a devicetree other than compiling it
into the single image we also add Colibri T20 on Iris support here
and add a defconfig for it.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There are more than Armada 370/XP in Marvell MVEBU SoC familiy. To avoid
irritation with source file nameing, we rename setup source file for
Armada 370/XP from core.c to armada-370-xp.c.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The SolidRun CuBox is a small cubic platform based on the Marvell
Dove SoC. There is nothing more than a console, yet.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit adds minimal support for the Marvell Dove SoC (88AP510) as
first SoC of the Marvell Orion family. Orion SoCs have a different timer,
therefore current mach-mvebu and Armada 370/XP Kconfig and Makefiles are
slightly modified and a new clocksource drivers is added.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Armada XP GP platform is an evaluation platform designed by
Marvell, that uses the MV78460 quad-core SoC from the Armada XP
family.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Mirabox is a platform manufactured by Globalscale, and based on
the Marvell Armada 370 SoC.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The OpenBlocks AX3 platform is manufactured by PlatHome and uses the
MV78260 dual-core SoC from the Armada XP family.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When a ARCH_MVEBU platform is selected, generate barebox.kwb and
barebox.kwbuart images from barebox.bin, using kwbimage.
barebox.kwb is generated by executing kwbimage on the board
kwbimage.cfg file, and is therefore designed to be booted from the
default boot media of the board, as defined by kwbimage.cfg (typically
a NAND flash or SPI flash).
barebox.kwbuart is generated by executing kwbimage on the board
kwbimage.cfg file, but by overriding the boot media to be UART. This
image is suitable for usage with the kwbtool and is generally useful
for recovery purposes.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Squashed this fixup:
arm: ensure the build doesn't fail when kwbimage lacks the binary blob
mach-mvebu images for Armada 370 and Armada XP SoC require a DDR3
training code which should be extracted from existing bootable images
for the relevant board. When such binary blob has not been extracted,
the build of the .kwb and .kwbuart images will fail. This is annoying
as it makes the build of all Armada 370/XP defconfig fail, which can
be a problem for automated builds.
This proposal makes the failure of kwbimage not a fatal failure for
the build process, and shows a warning. The user therefore sees:
====================================================================
KWB barebox.kwb
Didn't find the file 'plathome-openblocks-ax3-binary.0' in '/home/thomas/projets/barebox' which is mandatory to generate the image
This file generally contains the DDR3 training code, and should be extracted from an existing bootable
image for your board. See 'kwbimage -x' to extract it from an existing image.
Could not create image
WARNING: Couldn't create KWB image due to previous errors.
KWBUART barebox.kwbuart
Didn't find the file 'plathome-openblocks-ax3-binary.0' in '/home/thomas/projets/barebox' which is mandatory to generate the image
This file generally contains the DDR3 training code, and should be extracted from an existing bootable
image for your board. See 'kwbimage -x' to extract it from an existing image.
Could not create image
WARNING Couldn't create KWB image due to previous errors.
====================================================================
The only drawback is that barebox-flash-image, which normally points
to barebox.kwb, becomes a stale symbolic link.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit adds minimal support for the Armada 370 and Armada XP SoCs
from Marvell.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
See also:
commit eb84709192
Author: Sascha Hauer <s.hauer@pengutronix.de>
Date: Mon Mar 25 15:18:38 2013 +0100
clk: remove unused __clk_[get|put]
This is some unused code resulting from copying stuff from
the kernel. Remove it.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a pinctrl driver for the Tegra 20 line of SoCs. It only
supports the three basic pinconfiguration settings function mux,
tristate control and pullup/down control.
The driver understands the same devicetree bindings as the Linux one,
unimplemented pinconfiguration options will be ignored.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The missing 'break' statement lets look an i.MX23 like an i.MX28.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This partly reverts:
commit 697e02b74f
Author: Alexander Shiyan <shc_work@mail.ru>
Date: Tue Jan 22 15:08:31 2013 +0400
ARM: ccmx51: Remove SDRAM size settings
This patch removes SDRAM memory size setting from board due
to auto detect last one by ESDCTL.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The board originally configured the SDRAM controller for the
maximum size and detected the usable SDRAM size by reading the
board id. This became broken after switching to automatic SDRAM
size detection by reading back ESDCTL values.
This patch brings back the old behaviour.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some boards setup more memory than they actually have. The real memory
size can then be detected later for example by reading a board id.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In commit ad09b59f8b "ARM i.MX31: give
register base addresses a proper MX31_ prefix", the IOMUX GPR setup
to enable USBH2 was replaced with an incorrect source register.
Instead of reading the GPR register, USBOTG HWHOST is used as rmw source,
which contains 0x10020001.
Beside the intended GPR[11] setup ("Enable USBH2 signals on AudioPort 3 and
AudioPort6"), this erroneously also sets
GPR[28] enable USBOTG loopback
GPR[17] override DSR_DCE1 with USBOTG_DATA4
GPR[0] select FIR DMA requests instead of UART2 DMA
Beside breaking UART2, it probably also broke some UART1 and USB OTG setups.
Fix this and replace the address with the appropriate defines.
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The prefix/cleanup series
ad09b59f8ba8c63596674c53af062b
missed a few unprefixed IOMUXC_BASE define users. Fix these.
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch fix incorrect Kconfig symbols for MACH_FREESCALE_MX51_PDK,
MACH_FREESCALE_MX53_LOCO and MACH_FREESCALE_MX53_SMD.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Barebox do not have support for MACH_NXDKN, MACH_NXHMIBB,
MACH_NXEB500HMI and MACH_NXHX boards, so remove these symbols.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
OMAP_CLOCK_ALL is missing in Kconfig, so remove the "select" statement
and all other references to this symbol.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We PAGE_ALIGN the size in dma_alloc_coherent so do it also when free the memory.
Use PAGE_SIZE instead of magic numbers.
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since commit:
2ccd451 ARM i.MX28: change default watchdog reset method
the external reset via the reset pin is broken. That commit overwrites the
HW_CLKCTRL_RESET register with only WDOG_POR_DISABLE set, which results in
disabling the external reset.
This patch uses read-modify-write to set the WDOG_POR_DISABLE, leaving the
WDOG_POR_DISABLE untouched.
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Due to some changes in the framework a resource size of zero does not map
anything at all and it does it silently.
Defining the resource size for the MCI interface make it work again on the
Chumby.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This switches the iomux-v3 (found on i.MX25,35,51,53,6) to pinctrl
support. The old SoC specific API is kept for compatibility. The
pinctrl devicetree support is enabled automatically when OFDEVICE
support is available.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch includes no functional change. If a configurable DDRPLL_M
is required later, it should be set by the board instead of from here.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The *PLL_N values can be calculated from the OSC value. This patch
includes no functional change.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Taken from the Linux kernel, simplified and reworked to match barebox.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ODMdata tells us how much RAM is installed, so no need to define this at
the board level.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ODMdata tells us which UART to use for debugging purposes. This is
agreed upon in both the upstream Linux kernel and U-Boot, so do it the
same way in barebox.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
All Tegra20 boards have a common startup sequence. Also there is an
agreement on how to find out about the installed amount of RAM and other
information needed by early startup. So as there is really no need to do
any lowlevel stuff per board, we can just do it at the ARCH level.
This also enables the first stage loading of barebox by detecting the
currently running CPU and booting the main CPU cluster if neccesary.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently only implements system wide reset functionality.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Replace the ad-hoc clocksource implementation with a proper driver for
the Tegra 20 timer. This driver is able to do the required hardware
initialisation itself.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Only a basic set of clocks is supported. This is a temporary solution
and will go away as soon as the port of the Tegra common clock code from
the Linux kernel is ready to go.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We will follow the Linux kernel and go devicetree only for Tegra. This
doesn't prevent specific code for certain boards, but always requires a
valid DTB for all boards.
Also regenerate the AC100 defconfig to reflect this change.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
All available opensource tools and published BCT configurations use
0x10800 as the default textbase on Tegra 20.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tegra isn't a single architecture, but a collection of more or less
similar chip families. Introduce the same conf define as used in the
Linux kernel to differentiate between those families.
Currently we are only supporting the Tegra20 chip type.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tegras main CPUs are all ARMv7.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Tested-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Alexander Shiyan
Jan Weitzel
Markus Niebel
Philipp Zabel
Sascha Hauer
S. Fricke
wilhelm
Teresa Gámez
Steffen Trumtrar
Brian Lilly
Jan Luebbe
Juergen Beisert
Enrico Scholz
Lucas Stach
Nicolas Pitre
Sebastian Hesselbarth
Gregory Hermant
Thomas Petazzoni
Antony Pavlov
Alexandre Belloni
Andreas Pretzsch
Marc Kleine-Budde
Jean-Christophe PLAGNIOL-VILLARD