When building a special image from the original (compressed or
not) binary, to not overwrite KBUILD_BINARY.
This allows producing multiple images (such as MLO, UBL, ...)
from the (z)barebox.bin. In the case where no special image is
used, KBUILD_IMAGE is set to KBUILD_BINARY.
This patch was developed together with Sascha Hauer. Thanks!
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so we are smaller than the 256KiB reserved for barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so we are smaller than the 256KiB reserved for barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The IMX i2c driver is to be used by SOCs on both the ARM and PPC architetures.
Use a more neutral name for the structure, function names and #define.
The driver name is now "i2c-fsl".
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
struct mc13xxx is dereferenced to be able to use dev_info. This is
not necessary since the informations are not mc13xxx related but
3stack related.
- remove unneeded mc13892 raw version printout
- use printk for telling that the init sequence failed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If a second bootstream was used, there was a sanity check which was not
only wrong (using erasesize instead of writesize) but also superfluous
(we got the block from an existing cdev, so it must be in the flash
range). Simply remove it to make bcb work as expected.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a function to take the usbphy1 through its initialization procedure.
The imx6_usb_phy1_disable_oc function is needed at least on the sabrelite,
as the power design is faulty. The state on other imx6 boards is unknown,
therefore it is an extra function call at the moment.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tested with a m25p128 flash both in nand boot & spi boot.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Change clock init to allow early gpio access. Add support for 4460 clocks.
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
based on: [U-Boot] [PATCH v 4/5] omap4: support TPS programming
TPS62361 is the new power supply used in OMAP4460 that
supplies vdd_mpu.
VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies
vdd_iva. VCORE3 is not used in OMAP4460.
Signed-off-by: F. Gasnier fabrice.gasnier@cenosys.com
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now that __mmu_cache_* restore the registers they can be called
as regular C functions. Create a header file for them and use
C functions rather than inline assembly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Save/restore the registers used in __mmu_cache_* so that they can
be called as regular C functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
initrd_start need to be init to data->initrd_address and updated only if the
addr is invalid.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
All other linker generated files are there, too, so it seems logical
to put the map file there aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
If pbl support is enabled only zbarebox.bin was built, but
not the SoC specific images. Fix this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
use $< rather than barebox.bin directly
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
With pbl support enabled most boards need a pbl-y for their lowlevel
stuff.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
The existing nand_boot functions all do the same, so move it to
a common place. To be flexible enough for future boards the real
image size is used instead of hardcoded 256k.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Juergen Beisert <jbe@pengutronix.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
The flash header is needed for pbl support, so move it to
separate file to be able to add it to pbl-y
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Depending on the SoC a barebox.bin, barebox.netx, barebox.s5p, MLO image
is generated. With pbl support there now is an additional
arch/arm/pbl/zbarebox.bin image.
To help the user to determine which image should be flashed to his device,
generate a barebox-flash-image link.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Use the prefetch engine to improve NAND performance. The howto
is derived from the Kernel. Unlike the kernel we do not make
the access mode configurable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of passing several options into the nand register function
it is much more straight forward to just pass the platformdata.
While at it, rename the function to omap_add_gpmc_nand_device to
better describe what it does.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch prevents to stop the autoboot randomly for the CALAO MB-QIL-A9260.
Indeed on this board, there's no pull-up on the RX inputs for the DBGU, COM1 & COM2 serial port.
With pull-up enabled, there's no longer unwanted character received from these console (CONFIG_CONSOLE_ACTIVATE_ALL=y).
Signed-off-by: Gregory Hermant <gregory.hermant@calao-systems.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
if 0 is passed to at91_add_device_sdram autodetect the sdram size
The amount of available ram is determined by the SDRAMC_CR register.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On at91 we need to put the size to load is the sram at the 6th exception vector
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is needed by at91 to specify the size of the binary to load from the
bootrom when booting for non nor flash.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Today we only use the DBGU port
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This allows for creating a lzo compressed binary unsing the pbl.
Only copy the piggydata if needed.
Add CONFIG_PBL_FORCE_PIGGYDATA_COPY option
In some case we need to copy the PIGGYDATA as the link address
as example we run from SRAM and shutdown the SDRAM/DDR for
reconfiguration but most of the time we just need to copy the
executable code.
based on Sascha Hauer
Add compressed image support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This allows for creating a pre-bootloader binary for
- nand boot
- mmc boot
- compressed image
The pbl will be incharge of the lowlevel init if needed.
The barebox will skip it.
Import string functions from linux 3.4 (arch/arm/boot/compressed/string.c) and
implement a dummy panic.
For now on introduce dummy zbarebox* targets and c code that will contain later
the decompressor. This only implemeted on ARM.
This patch is based on Sascha Hauer <s.hauer@pengutronix.de>
Add compressed image support patch
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- dev_ready is supposed to return whether the device is ready or
not, not to poll until the device is ready.
- dev_ready should return true for ready and false for not ready
- waitpin polarity is not needed (at least the kernel does not have it)
- wait_mon_mask must be 32bit.
The code was unused since no board specified a wait pin, so no breakage
included. This also removes the now unused timeout variable from
platformdata.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX5 does not have a valid function to get the spi clock. This
patch introduces a function for i.MX6, and moves the bogus spi clock
speed to the speed-imx5*.c. Not nice, but preserves the current status
quo for i.MX5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Tiny6410 and its base board is a pure development platform.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
After adding the base support, the SoC can now be enabled in the build system.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The S3C64XX SoC has a real 32 bit counter, but almost the same style of
registers. It's enough to change the parameters, to get the routines work on
this SoC.
sha: s5p timer works like s3c64xx, so use #else to cover this.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
More or less just cosmetic (removing ifdefs!).
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The other SoCs differs in many ways from the currently supported S3C2410 and
S3C2440, so remove them.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Although the spi chipselects should really be const, there is no
good way to fix the compiler warning, so remove the const.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some drivers use gpio_request/gpio_free. Currently no architecture
has code behind these functions. Provide static inline functions
for these and remvoe the at91 specific inline functions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We need inline versions of armlinux_set* exactly when
CONFIG_ARM_LINUX is not set, because this is the symbol
used to compile the non inline versions.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This fix a clock inaccuracy in get_time_ns (used by sleep, time, etc).
At i.MX53 power-on GPT clock is typically 55500000 Hz, and it will be used
to calc the clock multiplier. After call imx53_init_lowlevel() GPT clock
will changed (e.g. to 66666666 Hz), but multiplier not. To fix this behavior call
clock_notifier_call_chain() after changing clock in imx53_init_lowlevel().
Signed-off-by: Wjatscheslaw Stoljarski <wjatscheslaw.stoljarski@kiwigrid.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
start.c has nothing to do with the exception vector table anymore,
so move it next to the exception handling code in exceptions.S
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Procedure is missing, so remove its declaration.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With compressed image support TEXT_BASE will become the base
address of the uncompressed image. What the boards want instead
is the base address of the decompressor code or, if not compressed,
the base address of the uncompressed image. Use _text which is
the correct one for both cases.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ep93xx needs a special value at offset 0x1000. Rather than
do special handling in the linker file add aa header section
as done on i.MX.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Calculating the offset between runtime and linked address makes the
intention of the binary copy function a bit more clear.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The exception vector table will become part of the uncompressed image,
so we can't reference them from the lowlevel init stuff anymore.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since commit 2f6b1f7690 the pull-up and
bitkeeper handling for i.MX23/28 is correct. But now it is important to
distinguish these pin features as their programmed bit values are different.
With this patch the bitkeeper and pull-up enable/disable bits are now handled
separately.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
A look into "arch/arm/boards/" offers various boards starting with the
vendor's name in their directory name (like 'eukrea' and 'freescale').
This patch does the same for the currently existing FriendlyARM board
Mini2440.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
This patch provide setup for SPI clk frequency global to driver.
For MC13783 maximum clock frequency is 20 MHz,
for MC13892 maximum clock frequency is 26 MHz,
so we define 20 MHz as a maximum SPI clk.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Here is a test output:
barebox 2012.07.0-00136-ge3ab4bc-dirty #23 Tue Jul 3 23:10:44 MSK 2012
Board: Phytec phyCORE-i.MX27
mc13xxx-spi@mc13xxx-spi0: Found MC13783 ID: 0x00009b [Rev: 3.1]
cfi_flash@cfi_flash0: found cfi flash at c0000000, size 33554432
NAND device: Manufacturer ID: 0x20, Chip ID: 0x36 (ST Micro NAND 64MiB 1,8V 8-bit)
Bad block table found at page 131040, version 0x01
Bad block table found at page 131008, version 0x01
imxfb@imxfb0: i.MX Framebuffer driver
cfi_protect: protect 0xc0080000 (size 1048576)
Using environment in NOR Flash
Found NXP ISP150x ULPI transceiver (0x04cc:0x1504).
ehci@ehci0: USB EHCI 1.00
imx-mmc@mci0: registered as mci0
Malloc space: 0xa6f00000 -> 0xa7efffff (size 16 MB)
Stack space : 0xa6ef8000 -> 0xa6f00000 (size 32 kB)
running /env/bin/init...
Hit m for menu or any other key to stop autoboot: 3
type exit to get to the menu
barebox@Phytec phyCORE-i.MX27:/ mci0.probe=1
mci@mci0: registered disk0
barebox@Phytec phyCORE-i.MX27:/ devinfo mci0
resources:
driver: mci
Card:
Attached is an SD Card (Version: 1.10)
Capacity: 1962 MiB
CID: 1C535653-44432020-1000013C-7E007200
CSD: 005E0032-5F5A83D5-2DB7FFBF-96800000
Max. transfer speed: 25000000 Hz
Manufacturer ID: 1C
OEM/Application ID: 5356
Product name: 'SDC '
Product revision: 1.0
Serial no: 81022
Manufacturing date: 2.2007
Parameters:
probe = 1
barebox@Phytec phyCORE-i.MX27:/ mkdir /d
barebox@Phytec phyCORE-i.MX27:/ mount /dev/disk0.0 fat /d
barebox@Phytec phyCORE-i.MX27:/ ls /d
barebox.bin
barebox@Phytec phyCORE-i.MX27:/
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This configuration can be used to use barebox as
x-loader replacement.
Also the ECC-Mode is changed from SOFT to BCH8.
Signed-off-by: Juergen Kilb <J.Kilb@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add reset to gpmc_generic_init as proposed by TRM.
This also fixes some strange timing issue while GPMC Initialization for
NAND OMAP4460
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Barebox crashes since it has trouble with a resource size of 0. Most of the
S3C24XX based platforms crashes at runtime and can't use devices with resource
sizes of 0 anymore. This patch fix it by unifying the device registration for
all current Barebox's S3C24XX based platforms.
- A9M2410 and A9M2440 compile time tested only.
- Mini2440 also runtime tested.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
While a set bit enables the pullup (if exists) it disables the bitkeeper (if
exists). Both features are using the same register bit and only one of this
feature is present on a per pin base.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We have the following in the tree:
|commit af42feb9d2
|Author: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
|Date: Mon Jan 2 11:49:17 2012 +0100
|
| ARM: set SCTRL[A] only when architecture does not support unaligned access
|
| Recent gcc generates code with unaligned access when architecture
| supports it. Setting A bit unconditionally causes data-aborts on such
| code rendering barebox unusable.
|
| Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
| Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
What the patch tried is correct: We should set the A bit only when the architecture
does not support unaligned accesses. To figure out whether the architecture supports
unaligned accesses the patch tested for the U bit which is wrong. The U bit may be
0 after a reset, so instead of testing for the U bit we have to set it. This can
be done on armv6 and later. All others have the A bit set to trap unaligned accesses.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This image header is used for booting from SPI using the TI User
Boot Loader (UBL).
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Jan Luebbe
Jan Weitzel
Jean-Christophe PLAGNIOL-VILLARD
Sascha Hauer
Renaud Barbier
Wolfram Sang
gregory hermant
Steffen Trumtrar
Eric Bénard
Alexander Shiyan
Juergen Beisert
Marc Reilly
Wjatscheslaw Stoljarski (Slawa)
Teresa Gámez
Alexey Galakhov
Juergen Kilb
Christian Kapeller
Maxime Ripard