Some SoC as sam9261 or sam9263 have enough sram to directly load a barebox
from external boot.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
the sam9x5 have multiple overlay but only register the base one
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
the sam9x5 have multiple overlay but only register the base one
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
add BAREBOX_MAX_IMAGE_SIZE and rebuild defconfig with savedefconfig
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as we will add later the GMAC IP verion support (GEM)
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This IP is present on the at91sam9 until the sam9g45, on the sam9x5 we use a
new IP.
This driver is based on the linux one.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
we have only 32MiB of sdram
by luck it was working
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On MIPS there are two segments in CPU address space that
can be used for untranslated memory access: KSEG0 and KSEG1.
KSEG0 is used for cached access and KSEG1 is used for
uncached one.
The instroduced mips_add_ram0() function registers two
address regions for memory access: one in KSEG0 and
the other one in KSEG1.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as it's handle by detecting the IP version and bus with
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Old cache/uncache pte flags were declared as defines.
Since these flags are determine at runtime they are static
variables.
This patch switch the naming style of these variables to
lower case which is typically used for variables.
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as the sam9260ek may not be the first one in the list
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as we will add the ihd before
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
the lowlevel init is the same as the usb-a9263 except that can not have the
128MiB option
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
v7_mmu_cache_flush stores registers on the stack and restores
them afterwards. Additionally v7_mmu_cache_flush is called
from v7_mmu_cache_off *after* disabling the MMU. With this
the following can happen:
- v7_mmu_cache_off disables the MMU. From now on no new values
go to the data cache.
- v7_mmu_cache_off calls v7_mmu_cache_flush which in turn puts
registers on the stack. Due to the MMU being disabled they
do not go into the data cache.
- In v7_mmu_cache_flush the memory the stack is pointing to is
overwritten with the values currently being in the cache.
- v7_mmu_cache_flush restores the registers from the stack with
values from the cache and not the memory where the values have
previously been written to.
Fix this by storing the registers on the stack *before* we disable
the MMU and restore them after we have called v7_mmu_cache_flush.
This way v7_mmu_cache_flush still restores corrupt register values
for the case when the MMU has been disabled, but we will restore
correct values afterwards.
This has been first observed when switching to gcc-4.7.2 when compiling
in Thumb2 mode, but could explain earlier problems also. The result
here was that the register holding the kernel address in start_linux()
was corrupted so that the kernel could not be started.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so we can add easly the console_none support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
warning: the ohci work only without MMU
enable:
- ehci
- usb strorage
- usb net asix
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
warning: the ohci work only without MMU
enable:
- ehci
- usb strorage
- usb net asix
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
LAN9221 is eth1, FEC is eth0, so fix power/reset control by
MC13892 GPOs.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch removes SDRAM memory size setting from board due
to auto detect last one by ESDCTL.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This will allow to boot from NAND/MMC and others.
This version of bootstrap is a non shell version of barebox compressed by the
pbl.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of hardcode define use a struct that the board fill
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so in bootstrap we do not compile it
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Hi Sascha,
I've made the changes you suggested in this resent patch.
Everything related to custom ATAGs has been moved to the board
directory.
The generic code does not make any references to feature lists or
bootloader versions.
About the setup_feature_list prototype:
it has been renamed to atag_appender
it's not a function, it's a pointer to a function. Can it have a
prototype other than it's own declaration?
All non-related changes has been dropped. They were checkpatch.pl
warnings unrelated to this patch.
Regards,
Vicente.
Signed-off-by: Vicente Bergas <vicencb@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The pattern for i.MX boards starting in external NAND boot mode is always
the same:
- Check if we are running in NFC address space, if not call
board_init_lowlevel_return()
- copy binary to link address
- execute relocated binary
- call imx_nand_load_image()
Add a common function for this to make the board code easier.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
environment.h is for environment variables, not for the environment
storage (envfs), so move the prototypes to envfs.h
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently Kconfig dependencies are used to allow non-interactive builds.
This leads to problems in Kconfig getting the dependencies right.
This patch adds a barebox_main function pointer which is called at the
end of the startup process. This defaults to run_shell when a shell is
enabled.
With this the HAVE_NOSHELL Kconfig variable can be removed. Non interactive
builds can now be enabled for every board allowing to compile a binary
without further Kconfig dependencies. This also allows for more flexibility,
for example boards may decide to try non-interactive startup first and
call run_shell if that fails.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This allows to register the USB ports for the chipidea driver. For
now the otg/h1 register functions also register the corresponding
USB phys.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
What we had as usb phy1 base address is really usb phy2. Fix the names
and add the missing base address definition for usb phy1.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The imx6_usb_phy1* functions are misnamed. It's usb phy2 that is configured
here, so rename the functions accordingly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When an oftree is already specified use it. This lets the user
boot a kernel with an oftree he provided himself rather than
hardcoding the concatenated one.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add barebox-data section in arm branch to get complete
barebox regions in sdram regions tree.
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The end of SDRAM is at 0x9fffffff, not at 0x8fffffff. This fixes starting
barebox when it is located in the second SDRAM bank.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
PAGE_ALIGN macro is needed to align addresses to page boundaries.
Move this macro to another PAGE_* defines.
Commands which uses remap_range function needs this macro.
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Change function remap_range in arm architecture to make it
global accessable. For example command 'memtest' can change
pte flags to enable or disable cache.
Add dummy function for others architectures that doesn't
have mmu or pte support.
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On the MX27 based board phycard-i.MX27 the display won't properly
come up.
Before removing imx-regs.h and the code that sets the register
in the i.MX video driver, the PCCR registers were set _after_
the screen start (LSSAR) was set.
This restores that old behaviour and makes the display come up
properly again.
I did not have a chance to test this on any other i.MX27 or i.MX21
hardware though I assume that the "old" order is required there
too.
Signed-off-by: Daniel Mierswa <d.mierswa@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Also put those names solely in the .c file as it's done with
the i.MX27 code.
Signed-off-by: Daniel Mierswa <d.mierswa@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
arch/arm/mach-at91/at91sam9g45_devices.c: In function 'at91_add_device_i2c':
arch/arm/mach-at91/at91sam9g45_devices.c:158:42: error: 'pdata_i2c' undeclared (first use in this function)
arch/arm/mach-at91/at91sam9g45_devices.c:158:42: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/mach-at91/at91sam9g45_devices.c:163:8: error: expected ':' or '...' before ';' token
arch/arm/mach-at91/at91sam9g45_devices.c:166:8: error: expected ':' or '...' before ';' token
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
We now have gpio_request. When we call gpio_direction_output before
registering a led_gpio the gpio will be implicitely requested by the
gpio core. gpio_request in the led core will then fail resulting in
an unregistered LED.
Fix this by removing the call to gpio_direction_output. The LED core
will do this anyway.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a function to register the cpws device and another one
to register the MAC addresses provided by the am33xx.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With bootm of_fix_tree() will already be called from the generic bootm
code, so do not do this again in the Android image handler.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Currently the bootm code uses of_fix_tree to apply the fixups
to the devicetree given on the command line. This function assumes
that there is enough space for the fixups available. Also on ARM
we have to make sure the tree does not cross 1Mib boundaries.
This patch moves the space allocation and alignment ensurance
to of_get_fixed_tree and uses it in bootm. This is the first
step for making of_get_fixed_tree the single point of devicetree
handling in barebox.
of_get_fixed_tree now takes an argument of the input fdt. If it is
given, this one is used, otherwise an internal oftree is used which
will be created in subsequent patches.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The am33xx hsmmc controller is actually a omap4 type controller which
means that it has a 0x100 offset in the registers.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Only the OMAP4 has a register offset of 0x100 in the register space. Fix
this by using the device id mechanism. This became broken when the device
register convenience functions were introduced.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This will allow to dump all pin configuration in a nice table
and if the bank/pin is specified the pin details
barebox@Atmel at91sam9x5-ek:/
Pin PIOA PIOB PIOC PIOD
0: [gpio] set [periph A] [gpio] set [periph A]
1: [periph A] [periph A] [gpio] set [periph A]
2: [gpio] set [periph A] [gpio] set [periph A]
3: [gpio] set [periph A] [gpio] set [periph A]
4: [gpio] set [periph A] [gpio] set [gpio] clear
5: [gpio] set [periph A] [gpio] set [gpio] set
6: [gpio] set [periph A] [gpio] set [periph A]
7: [gpio] set [periph A] [gpio] set [periph A]
8: [gpio] set [gpio] set [gpio] set [periph A]
9: [periph A] [periph A] [gpio] set [periph A]
10: [periph A] [periph A] [gpio] set [periph A]
11: [periph A] [gpio] set [gpio] set [periph A]
12: [periph A] [gpio] set [gpio] set [periph A]
13: [periph A] [gpio] clear [gpio] set [periph A]
14: [gpio] set [gpio] clear [gpio] set [gpio] set
15: [periph A] [gpio] set [gpio] set [gpio] set
16: [periph A] [gpio] set [gpio] clear [periph A]
17: [periph A] [gpio] set [gpio] set [periph A]
18: [periph A] [gpio] set [gpio] set [periph A]
19: [periph A] [periph A] [gpio] set [gpio] set
20: [periph A] [periph A] [gpio] clear [gpio] set
21: [gpio] set [periph A] [gpio] clear [gpio] clear
22: [gpio] set [periph A] [gpio] set [periph A]
23: [gpio] set [periph A] [gpio] set [periph A]
24: [gpio] set [periph A] [gpio] set [periph A]
25: [gpio] set [periph A] [gpio] set [periph A]
26: [gpio] set [periph A] [gpio] set [periph A]
27: [gpio] clear [periph A] [gpio] set [periph A]
28: [gpio] set [periph A] [gpio] clear [periph A]
29: [gpio] set [periph A] [gpio] set [periph A]
30: [gpio] set [periph A] [gpio] set [periph A]
31: [gpio] set [periph A] [gpio] set [periph A]
barebox@Atmel at91sam9x5-ek:/
pioA27 configuration
[gpio] clear
multidrive = disable
pullup = disable
degitch = disable
debounce = disable
pulldown = enable
schmitt trigger = enable
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
to select the smc and timer for at91sam9 soc
This will allow to simplify the Makefile
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This will allow to support multiple arch
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
and then register a device
The code is take from linux
drop AT91_BASE_SYS for dbgu
factorise the soc type in the Kconfig but keep the ARCH_ so far
as the device code have the same function accross soc which for now does not
allow us to compile soc together
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
add non AT91_SYS_BASE offset base address define
This will prepare for multi arch support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so we can drop AT91_BASE_SYS too
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as d1 pioB18 is used for the one wire too
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
imported from the kernel
this allow to simplify the mux implemtation and will simplify the gpio support
from bare_init or pbl
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this is the first step to prepare the switch to the gpiolib
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so 0 is a valid gpio as cleanned in the kernel
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
switch gpio type from u8 to int in the data struct
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
MC34708 depend on I2C or SPI, so let driver depend on SPI too
and rename config option name to MFD_MC34708.
Signed-off-by: Wjatscheslaw Stoljarski <wjatscheslaw.stoljarski@kiwigrid.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Created ARCH for AM33xx boards as second stage bootloader.
This includes:
- Added dmtimer0
- Created basic header files
- Added MMC support for ARCH_AM33XX
- Added reset function
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Some header file cleanup by:
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The hsmmc module has a 0x100 offset in its register space. The real
register space size for the module is 4K, so when we register the
device with the size 4k, we have to account for the offset in the
driver, not in the resource allocation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- remove mach/silicon.h and include omap?-silicon.h directly
- include mach/omap?-clock.h directly where needed
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARCH_OMAP2 missing in barebox.
ARCH_OMAP3 and ARCH_OMAP4 is only choice for this target.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Efika MX Smartbook is a i.MX51 based netbook. This patch adds
nearly full support for it including:
- USB
- SD card slots
- Internal SPI NOR flash
- Internal flash PATA drive
- LEDs
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The board variant found on the AT24 EEPROM holds the variant ID that we
can use to identify which expansion board we are running on and thus
which device tree to load and pass to the kernel.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The AT24 found on the expansion boards store the variant of the board it
is soldered onto.
That means that we are that way able to determine what expansion board
is currently plugged in if any. If we can't communicate with the EEPROM,
we just assume that only the CFA-10036 is there.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This EEPROM is found on the expansion boards available for the 10036
module. Since we won't need to do anything fancy except reading/writing
from it, use bitbanging to communicate with it.
This EEPROM will hold mostly the board_id so that we can determine if
there is an expansion board plugged in and what expansion board it is.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Trivial pbl support has no cpu specific setup.
We will add cache setup routines in the future.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch is based on ARM pbl support and allows
creating a pre-bootloader binary for compressed image.
For different MIPS SoCs (or even for different boards based
on the same SoC) the operations carried on in start-pbl.S
can be very different. The additional constraints can be imposed
on the size of the boot code or the special magic labels in
the beginning of the boot code; In some cases it could be
necessary to show CPU is alive as early as possible
(transmit a char via UART or blink a LED).
So the demands for pbl start operation can be very different.
E.g. malta board store boot code at the NOR flash mapped
to the MIPS power-on address (0xbfc00000); it is the most
simple case: we need just copy pbl image from direct-mapped
flash to RAM and jump there.
The XBurst-powered boards store boot code in the beginning
of a NAND flash or in the beginning of SD/MMC card.
In this case we must use simple and short NAND or SD/MMC access
routines to copy pbl image to RAM.
To meet so different demands a simple technique is selected:
* MIPS pbl entry point located in file arch/mips/boot/start-pbl.S.
* MIPS pbl code (see start-pbl.S) assumes that every pbl-enabled
board has a arch/mips/boards/<BOARD>/include/board/board_pbl_start.h
header file. This file must contain definition of
the board_pbl_start macro. This macro is used as start of pbl image;
* the most popular asm routines (stack setup, relocation to link
address, NS16550 initialization (WIP) and so on) are containt
in the arch/mips/include/asm/pbl_macros.h header file.
So board pbl macro can use it if necessary.
It is possible to create similar headers with macros for each
specific SoC; so even if we have many different boards based
on the same SoC the board_pbl_start macro for every board
can be short and clear.
* after board-specific initialization the stack pointer
is initialized and pbl C code is started.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ULPI lines are normally input to the USB port. In order to configure
the ULPI transceiver properly the ongoing transfers must be stopped. This
can be done by configuring the the STP pin as gpio output and drinving
it high.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Jean-Christophe PLAGNIOL-VILLARD
Jan Weitzel
Antony Pavlov
Fabio Porcedda
Sascha Hauer
Alexander Aring
Alexander Shiyan
Vicente Bergas
Daniel Mierswa
Jan Luebbe
Wjatscheslaw Stoljarski (Slawa)
Teresa Gámez
Maxime Ripard