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Author SHA1 Message Date
Alexander Shiyan 9a4cb25a39 treewide: Reuse init_clock() return value for clocksource drivers
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-11-10 08:42:19 +01:00
Lucas Stach 566c1630c3 tegra: remove custom UART setup
The config option doesn't make any sense anymore
when building a multiimage barebox. With a proper
DT built into the image we don't need the ODMdata
mechanism to find the debug UART anymore.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-11-04 12:16:52 +01:00
Lucas Stach 1834169f13 tegra: pmc: add support for reset src detection
Also activate in defconfig.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-11-04 12:16:40 +01:00
Lucas Stach a546e66838 tegra: jetson-tk1: enable 1.05V_RUN
Needed for the PCIe PLL amongst other things.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-11-04 09:50:43 +01:00
Lucas Stach 7cf0a3ea2b tegra: pmc: work around power domain failure
Sometimes a power domain didn't properly power up,
reading back the command register seems to fix this
by flushing the write.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-11-03 09:38:37 +01:00
Lucas Stach 7a2255b43e tegra: pmc: add powerdomain handling
In order to use some devices we first have to power
up their power domain. Add support to do this in a
generic way.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-10-08 08:39:01 +02:00
Lucas Stach 72f493e3e6 clk: tegra30: add PCIe clocks
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-10-08 08:39:01 +02:00
Lucas Stach aa2e6ca831 clk: tegra: add PLLE setup functions
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-10-08 08:39:01 +02:00
Sascha Hauer fa93e4fb60 Merge branch 'for-next/resource-err-ptr' 2014-10-02 08:54:42 +02:00
Sascha Hauer ed6e965824 resource: Let dev_request_mem_region return an error pointer
For all users fix or add the error check.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-09-16 08:32:10 +02:00
Sascha Hauer 92fd6af347 pinctrl: fix Kconfig dependencies
- Remove OFDEVICE dependency from PINCTRL. It won't do
  much then, so add a comment to Kconfig when PINCTRL is
  selected without OFDEVICE
- Let Architectures only select PINCTRL instead of the
  particular driver. Change the drivers to 'default y if $SOC'
  to make sure the drivers are still compiled if the corresponding
  SoC is selected

This fixes Kconfig warnings like:

warning: (PINCTRL_ARMADA_370 && PINCTRL_ARMADA_XP && PINCTRL_DOVE && PINCTRL_KIRKWOOD) selects PINCTRL which has unmet direct dependencies (OFDEVICE)

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-09-15 07:17:06 +02:00
Lucas Stach db158af8cd arm: tegra: enable ARM errata workarounds
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-26 08:05:21 +02:00
Lucas Stach a2226db2d2 tegra: add NVIDIA Jetson-TK1 board support
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:15 +02:00
Lucas Stach 77b9a2120c tegra: pmc: add Tegra124 compatible
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:15 +02:00
Lucas Stach 8d9cbe17d3 pinctrl: tegra: add Tegra124 support
We can reuse the Tegra30 pinctrl driver, as the bit
layout is the same. Just add the pin and drivegroups
and some compile-time magic to avoid bloat.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 65c962feb5 tegra: add Tegra124 Kconfig symbol
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 9a13c92e5a tegra: add architectural timer init
If the bootloader doesn't init the architectural timer
on Cortex A15 Linux falls over when trying to boot.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 22920598a5 tegra: setup L2 cache on Tegra124
Set SRAM latency to 3 clock cycles.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 08f5fcbad6 tegra: hardcode entry address for main cluster
I don't know why get_runtime_offset fails on T124 yet,
but this is a safe workaround, with the nice side-effect
of fixing second stage barebox loading.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 8dc05ab677 tegra: apply cluster switch logic to all SoCs >=T30
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 566fd492ab tegra: add Tegra124 PLL_X rate setup
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 983f39f6ca tegra: change cpu internal reset layout for Tegra124
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 3d6fcedfeb tegra: fix MESLECT clock enable
Don't disable clk to unrelated devices in the process.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 3e5f060696 tegra: power up additional partitions on Tegra124
Those 3 are needed to power CPU0 from the CPUG cluster.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 3cc59d0e21 tegra: disable IDDQ for PLL_X on Tegra124
This is an additional power down control.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach acef7b8f3d tegra: add Tegra124 and AS3722 PMIC to lowlevel-dvc
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 858e703f8c tegra: recognize Tegra124 in common initcalls
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach e11e7d9a15 tegra: recognize Tegra124 in maincomplex startup
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach c8e61fa978 tegra: lowlevel: fix ODMdata fetch on Tegra124
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach ff5f8ef49a tegra: add Tegra124 id to lowlevel functions
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 7819300000 tegra: lowlevel: setup an early stack
Even the lowlevel functions are growing to a
size where having a stack seem beneficial.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach a41187b2e9 tegra: pmc: add command to get into RCM
In RCM aka recovery mode the BootROM waits for a
usbloader to take over control. On most boards this
is triggered by holding a physical switch which may
be inconvinient at times. Add a command to switch
into RCM from software.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-05 08:01:14 +02:00
Lucas Stach 7b8f46983e tegra: pmc: add Tegra30 compatible
Allows reset command to work on T30.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-04 07:21:18 +02:00
Lucas Stach a369af31dc tegra: lowlevel-dvc: use __always_inline macro
Cleaner code.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-06-04 07:21:17 +02:00
Lucas Stach 5f2965cc80 ARM: tegra: beaver: activate sdmmc1 voltage rail
In order to get the SD card solt working.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-15 14:17:12 +02:00
Lucas Stach 86a752954b clk: tegra30: register i2c clocks
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-15 14:17:12 +02:00
Lucas Stach 7a9d497860 tegra: lowlevel: add function to fetch chipid
This is needed as a safe way to flush the ABP bus.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-15 14:17:11 +02:00
Lucas Stach fb6e4db3ce ARM: tegra30: ramp vdd_core to 1,2V
This isn't much different from the default 1,16V
and I haven't seen this make a difference on any
board, but it seems to be required for some T30 SKUs.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-08 09:35:50 +02:00
Lucas Stach acbecd1987 ARM: tegra30: slow down CPU to 600 MHz
It's not safe to ramp up the CPU clock speed to
1,4 GHz on all T30 SKUs, as this may result in failure
to start the kernel properly. Start CPU at 600 MHz,
which is safe even for the slowest SKUs.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-08 09:35:50 +02:00
Lucas Stach 4f381b1aaa ARM: change signature of barebox_arm_entry
Mostly to make it clear that boarddata needs to be
something we can dereference.

As this is a pretty invasive change, use the opportunity
to make the signature 64bit safe.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-05-05 15:09:09 +02:00
Sascha Hauer 7b7631791e Merge branch 'for-next/tegra'
Conflicts:
	arch/arm/dts/tegra20-colibri.dtsi
	arch/arm/dts/tegra20-paz00.dts
	arch/arm/dts/tegra20.dtsi
	drivers/clk/tegra/clk-periph.c
2014-05-05 13:34:21 +02:00
Lucas Stach 3a1934eaa9 ARM: tegra: add NVidia Beaver board support
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:40:59 +02:00
Lucas Stach f09394ab1a pinctrl: tegra: add Tegra3 driver
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:39:57 +02:00
Lucas Stach e61f9e458d tegra: recognize T30 in debug UART code
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:39:14 +02:00
Lucas Stach fa94149a5b tegra: add Tegra3 mem initcall
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:39:14 +02:00
Lucas Stach 90542372c4 tegra: add Tegra3 ramsize detection
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:39:14 +02:00
Lucas Stach cdc5b61c6d tegra: add Tegra3 kconfig symbol
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:39:14 +02:00
Lucas Stach 0fe976103e tegra: source MSELECT clock from CLK_M
We need to reprogram PLL_P at a later time, so
we have to make sure MSELECT is able to operate
correctly when we stop PLL_P.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:39:14 +02:00
Lucas Stach bd4cbd927c tegra: disable more lowlevel unsafe switch optimizations
fno-jump-tables isn't enough to guard against
gcc switch optimizations that are unsafe to use
in code that runs before relocation.

The switch-tree-conversion opt pass may generate
lookup tables that are placed in the data section
and accessed via absolute adressing, which fails
prior to relocation.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-23 11:39:13 +02:00
Michel Stam 9f556d4b6f x86: ns16550: Rework driver to allow for x86 I/O space
The current implementation fakes a memory-mapped I/O device
at 0x3f8 and 0x2f8, then uses platform read/write functions
to do the actual reading and writing. These platform functions
only exist for the x86 platform; better to move the I/O
routines into the driver and have the driver request I/O ports
using request_ioport_region.

Signed-off-by: Michel Stam <michel@reverze.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-04-09 19:31:42 +02:00