nand.c issues a warning when imx_nand_set_layout is
empty. We don't need this function on i.MX53, so
silence the warning.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The S3C2440 CPU comes with an internal OHCI the generic part of
Barebox already supports. Just add the missing part.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently, there are multiple definitions of run_shell()
for each board that can be build in "xload" configuration.
Now there is only one function used by all boards.
The functions defined in xload.c are used only when "xload"
configuration used; but it gets compiled unconditionally.
This has been fixed as well.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If the user has parsed a tree, we start Linux using the
device tree, otherwise we use the traditional ATAG
mechanism.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When building sandbox with ccache, one would hit warnings such as:
warning: 'struct mmsghdr' declared inside parameter list
on random files; a way to reproduce this issue is to build a simple
file doing just:
#include <sys/socket.h>
int main(void) {
return 0;
}
gcc -Wall -P -c -o foo foo.c
But actually the -P flag is only useful when generating non-C files,
such as linker scripts in the case of barebox. Removing the -P flag
from all the gcc invocations, except when generating .lds files makes
the warning go away. It turns out that this is what
linux/scripts/Makefile.build also does nowadays.
Signed-off-by: Loïc Minier <loic.minier@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Running the 'bootz' command always fails with
could not read <some file>
due to wrong usage of pointers and structures. This is the second try to fix
the 'bootz' command. At least on my target it is now be able again to load a
kernel without any error.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Running the 'bootz' command always fails with
could not read <some file>
due to it loads only a size of a pointer, instead of the size of the expected
header structure.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Contrary to other Atmel boards, the AT91SAM9M10G45EK board file only
describes the case where NAND is used as the storage for Barebox and
its environment. Therefore, it makes sense to enable the Atmel NAND
driver in the default configuration for this board.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The environment partition was overlapping the Barebox partition in
those three Atmel boards. Saving the environment resulted in the
Barebox being overwritten.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We switched to resources recently and the nand controller
of the i.MX53 needs two of them, so fix the helper in the
same way as the i.MX51
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds lowlevel (AIPS, PLL, L2) initialization for i.MX53 boards.
This is a direct transcription of Freescales U-Boot assembler code
with the exception that we initialize PLL1 with 1000MHz and assume
that all necessary voltages are already adjusted when we arrive here.
It must be explicitely called from the boards so a board is free to
do it's own initialization. However, boards should use this code
and make it more configurable if necessary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fixes alignment for the "System Type" menu entry.
Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tested on imx53 loco board with a Multi uImage file
generate like this
mkimage -A arm -O linux -T multi -C none -a 0x70008000 -e 0x70008000 -n Linux-2.6.35.3-00745-gce4c61a-dirty -d zImage:rootfs.cpio.lzma uImage.Multi
and boot via bootm
bootm -r @1 -L 0x72000000 /dev/ram0.kernel
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This fixes the following compile errors
arch/arm/mach-at91/at91sam9g45.c:185:3: error: 'ohci_clk' undeclared here (not in a function)
arch/arm/mach-at91/at91sam9g45.c:186:3: error: 'tcb1_clk' undeclared here (not in a function)
arch/arm/mach-at91/at91sam9g45_devices.c: In function 'at91_add_device_mci':
arch/arm/mach-at91/at91sam9g45_devices.c:258:2: warning: implicit declaration of function 'at91_clock_associate'
[...]
arch/arm/mach-at91/built-in.o: In function `at91_add_device_mci':
sam9_smc.c:(.text.at91_add_device_mci+0x1d0): undefined reference to `at91_clock_associate'
arch/arm/mach-at91/at91sam9260_devices.c: In function 'at91_add_device_mci':
arch/arm/mach-at91/at91sam9260_devices.c:251:2: warning: implicit declaration of function 'at91_clock_associate'
which were introduced in commit:
"at91: swtich to clkdev" (ae19fe26cc)
Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This brings consistency to the way variables are named and used
according to the Freescale documentation. Also, since user is
supplying row indicies, and not offsets, it's reasonable to amend the
error message accordingly.
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds additional Kconfig help to clarify the way to use barebox
for eFuses handling.
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
By doing this we can remove the ptes field in struct arm_memory
which won't be present in a generic memory bank structure anymore.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To allow for some generic io accessors introduce io.h and use
this instead of asm/io.h throughout the tree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The nand controller on i.MX51/53 uses two base addresses. Instead
of hardcode the second address use the new shiny resources two specify
it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Based on the Linux driver. Tested with m25p80 with CS in GPIO mode.
Clock setting support is ad-hoc as the corresponding mach is not using
the generic clock infrastructure.
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This fixes the following compile errors
arch/arm/mach-at91/at91sam9g45.c:185:3: error: 'ohci_clk' undeclared here (not in a function)
arch/arm/mach-at91/at91sam9g45.c:186:3: error: 'tcb1_clk' undeclared here (not in a function)
arch/arm/mach-at91/at91sam9g45_devices.c: In function 'at91_add_device_mci':
arch/arm/mach-at91/at91sam9g45_devices.c:258:2: warning: implicit declaration of function 'at91_clock_associate'
[...]
arch/arm/mach-at91/built-in.o: In function `at91_add_device_mci':
sam9_smc.c:(.text.at91_add_device_mci+0x1d0): undefined reference to `at91_clock_associate'
arch/arm/mach-at91/at91sam9260_devices.c: In function 'at91_add_device_mci':
arch/arm/mach-at91/at91sam9260_devices.c:251:2: warning: implicit declaration of function 'at91_clock_associate'
which were introduced in commit:
"at91: swtich to clkdev" (ae19fe26cc)
Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
from linux
commit 8251544f9e28058e54c4f35b7cd13b0d191d7555
Author: Ryan Mallon <ryan@bluewatersys.com>
The uhpck clock should be divided from the utmi clock, not its parent
(main). This change is mostly cosmetic as the uhpck rate value is not
used anywhere except for the debugfs clock output.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
so we can dynamise the boot depending on the machine
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Commit c71a77ab8 (ns16550: switch to resource) has introduced generic
read/write access to 16550 register and a 'shift' parameter to allign
register index to physicall registers.
The correct 'shift' value was missing in all omap based boards.
Corrected this to 2 which has fixed the problem.
Tested on a PCM-049 phyCORE-OMAP4 board.
Signed-off-by: Juergen Kilb <J.Kilb@phytec.de>
Tested-by: Jan Weitzel <J.Weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This helper function can be used for automatic
SDDR configuration based on register settings
made by a previously first stage bootloader
i.e. x-loader.
Signed-off-by: Juergen Kilb <J.Kilb@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add platform data to specify maximum frequency of hsmmc interface
which can be restricted due to external level shifters.
Signed-off-by: Juergen Kilb <J.Kilb@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
commit 7d25a0552dd3a4b65412ae1cbf8f9ca8a88b5d27
Author: Juergen Beisert <jbe@pengutronix.de>
Date: Thu Nov 25 17:49:11 2010 +0100
Keep frequency multiplier enabled to be able to do a warmstart
The wachtdog's reset does only reset the ARM core, not the whole silicon.
But the PLLs seems to do some strange things: It seems they switch back to
the low frequency reference when the watchdog barks. But in the case the
frequency multiplier is off (not used due to 26 MHz reference usage) the
machine stops, because the PLLs are stopping due to the lack of a reference
frequency. As the power on reset will set the FPM_EN bit again, a power cycle
brings the machine back to life.
By keeping the frequency multiplier enabled, also a warmstart triggered by the
watchdog can restart the machine now.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
According to the datasheet, PUE is not effective without PKE set.
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Set new CS0 values for new NOR-Flashes (28F256P33BF).
These values also work with older flashes (28F256P33B).
Also removed unnecessary setup of CSO in the core_init call.
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0".
This changes write recovery from 8 clocks to 6 clocks(in line with ESDCFG1[tWR])
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
These images have to be located in the first 128MB of SDRAM, so
use the following strategy:
- first try to map the image. If the pointer is within the first
128MB of sdram everything is fine.
- if we can't map the image, check for SDRAM being smaller than
128MB we can use malloc for allocating space for the image.
- As a last fallback we simply put the image to 8MB into SDRAM.
This is not very clean. We try our best by checking that we
won't overwrite the malloc space.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some older pcm043 only work correct when cpu frequency is set up
to 399MHz. All modules with revision >= 1315.4 are equipped
with a i.MX35 TO2.1 and do run with 532MHz.
Check the silicon revision and set up the frequency accordingly.
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now that env_push_context is in a coredevice_initcall
we can initialize barebox_loc earlier so that we can
use it inside later initcalls.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer <s.hauer@pengutronix.de> wrote ..
> On Thu, Aug 11, 2011 at 02:37:05PM +0400, Alexander Shiyan wrote:
> > Hello.
> >
> > Please review and apply this simple patch.
...
> Please remove the #ifdef CONFIG_I2C
OK.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as we need to register it before the device
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as we need to register it before the device
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this will also fix the clock support as we now switch to allocated generic
device
as we can need to associate the clock and the device but the driver is probe
before the association
we also change the atmel serial name to "atmel_usart" to simplify sharing with
linux
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- Don't call panic with "resetting CPU...". Depending on the
configuration the system might also hang.
- panic does not return, so no need to call reset_cpu afterwards
- bundle show_regs and panic into a seperate functions to not have
to call both functions from each exception handler
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The exception vector at 0x14 is not used on arm, so no need
to bind this address to a exception handler. Remove the
corresponding code
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In barebox we used 1MiB sections to map our SDRAM cachable. This
has the drawback that we have to map our sdram twice: cached for
normal sdram and uncached for DMA operations. As address space gets
sparse on newer systems we are sometines unable to find a suitably
big enough area for the dma coherent space.
This patch changes the MMU code to use second level page tables.
With it we can implement dma_alloc_coherent as normal malloc, we
just have to remap the allocated area uncached afterwards and map
it cached again after free().
This makes arm_create_section(), setup_dma_coherent() and mmu_enable()
noops.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The new MMU setup will need SDRAM base addresses and sizes.
For this reason convert the MMU enabled ARM boards:
- move mem setup to mem_initcall. This is early but
still makes sure that we already have the console available
- move MMU setup in this initcall temporary as after the mmu_init will generic
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
We want to use the memory banks later in the MMU which is
independent of Linux, so move this to a location which is
always compiled.
Also, make the memory bank list global and add an iterator
for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
use generic read/write depending on the memory size
if no reg_read/write defined
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
...and update all users. The header file can be used on mx51 and mx53.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The register based fuse readout is not available on i.MX27/31
SoCs, so make explicit sensing the default.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Do not depend on the specific SoCs for the IIM module, but
instead exclude the one that don't have this unit.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The IIM module uses two drivers, one for the general IIM
module and one for the individual banks.
This patch turns this into a single driver to ease registration
of the resources. This changes the user visible behaviour in
the way that the explicit_sense_enable and permanent_write_enable
device parameters are no longer bank specific but for the
whole device. Also, the IIM module supports a maximum of
8 fuse banks, with these patch all of them are registered, even
if they are not present in a SoC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
pass the hccr and hcor register base via resource
instroduce add_generic_usb_echi_device with hccr = base + 0x100 and
hcor = base + 0x140
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Add a helper function for boards to register their memory
devices. This makes the board code smaller and also helps
getting rid of map_base and struct memory_platform_data.
And switch all of the memory to it
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
we keep struct memory_platform_data for now on we will switch off the memories
resources to struct resource
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)
so we will match the erase block size
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When the bus_width was set to 8, then only one data-line has been initialized.
Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
MLO is to big (>40000) to save Space disable CONFIG_FS_RAMFS and
CONFIG_FS_DEVFS in defconfig
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If booting from NAND GPMC_IRQ_ENABLE is not cleared, causing crash if kernel
request the gpmc irq. gpmc_generic_init clears GPMC_IRQ_ENABLE
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Heavily based on original Juergen Beisert's code.
Signed-off-by: Alexey Galakhov <agalakhov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is useful to detect a barebox image and to be able
to copy only the image size if barebox is stored on
raw partitions which are bigger than the image.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix following warning:
arch/arm/boards/karo-tx25/lowlevel.c: In function 'board_init_lowlevel':
arch/arm/boards/karo-tx25/lowlevel.c:75:6: warning: unused variable 'i'
Signed-off-by: Marek Belisko <marek.belisko@open-nandra.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix following warning:
arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c: In function 'eukrea_cpuimx35_devices_init':
arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c:176:15: warning: unused variable 'tmp'
Signed-off-by: Marek Belisko <marek.belisko@open-nandra.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If OMAP4 fall back to MMC1 boot in bootmode 0x39 (NAND,USB,UART,MMC1)
NAND and MMC bit in TRACING_VECTOR3 are set. With changed order it will
detect boot from MMC.
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add some common xload helper functions to determine the boot source
on omap3/4 and to load images from mmc and nand.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On several boards without MMU support the vectors cannot be mapped
to 0x0 and exception support is nonfunctional anyway, so make this
configurable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds BCH ecc support to the omap nand driver. The BCH
error correction allows for up to 8 bit error correction. It is
also needed for booting from nand on omap4.
This is based on code from Sukumar Ghorai <s-ghorai@ti.com>:
[PATCH] omap3: nand: bch ecc support added
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On omap we use different ecc modes for different purposes. The initial
boot code has to be written with hardware ecc whereas Linux usually uses
software ecc. To be able to write in both modes with a sinlge barebox
image introduce a eccmode device parameter.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If compiled without gpio support the linker will throw the
gpio functions away anyway, so make the omap kconfig entries
a bit easier.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Give this omap specific entry an omap namespace. Also, remove
unnecessary dependency to omap2/3 in nand Kconfig.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The original plan was to add all omap devices into the boards/omap
directory. Anyway, there will be reasons to put a board somewhere
else, so move the generic parts into the omap architecture directory.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current gpio support is derived from the kernel which allows
for support for omap2/3/4 in a single kernel. We do not need this
here, so make it more simple to be able to add omap4 support later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When booting from NAND, its important to know the correct page size. When
the NAND is used as the boot source, four dedicated pins are used to configure
the correct page size and address cycles. These pins can be read back in one
of the NFC registers to parametrize the load function.
This patch also extends the read routine to support more than four address
cycles on demand.
BTW: At least some mini2440s are misconfigured to use five address cycles for
a NAND device that is known to need only four address cycles. In this case the
vendor is at our side: This NAND simply ignores any additional address cycles
than required.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
before we can only support tftp
so keep it as default
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)
so we will match the erase block size
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Often enough the exception vectors are not on TEXT_BASE (for example
on i.MX SoCs in internal boot mode), so the board specific code did
not map the exception vectors to 0x0 but whatever happens to be on
TEXT_BASE. Also, the current section-only mapping requires the
exception vectors to be on a 1MB boundary.
Instead, create the possibility to create second level tables and
use this to map a copy of the exception vectors in a board
independent way.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The armv7 specific __mmu_cache_on function accidently sets
the page table pointer with the unitialized value of r3. It seems
that often enough r3 still held the correct value from a previous
call to mmu_init allowing this bug to remain uncovered for longer.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To prevent turning on the display before the signals are stable.
Also, put the LCD_CS pin in the same mode as the kernel does to
prevent flickering.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
