Some older pcm043 only work correct when cpu frequency is set up
to 399MHz. All modules with revision >= 1315.4 are equipped
with a i.MX35 TO2.1 and do run with 532MHz.
Check the silicon revision and set up the frequency accordingly.
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now that env_push_context is in a coredevice_initcall
we can initialize barebox_loc earlier so that we can
use it inside later initcalls.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha Hauer <s.hauer@pengutronix.de> wrote ..
> On Thu, Aug 11, 2011 at 02:37:05PM +0400, Alexander Shiyan wrote:
> > Hello.
> >
> > Please review and apply this simple patch.
...
> Please remove the #ifdef CONFIG_I2C
OK.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as we need to register it before the device
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
as we need to register it before the device
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
this will also fix the clock support as we now switch to allocated generic
device
as we can need to associate the clock and the device but the driver is probe
before the association
we also change the atmel serial name to "atmel_usart" to simplify sharing with
linux
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- Don't call panic with "resetting CPU...". Depending on the
configuration the system might also hang.
- panic does not return, so no need to call reset_cpu afterwards
- bundle show_regs and panic into a seperate functions to not have
to call both functions from each exception handler
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The exception vector at 0x14 is not used on arm, so no need
to bind this address to a exception handler. Remove the
corresponding code
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The only supported peripheral is ns16550 serial port.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The machine uses only big-endian mode.
Only supported peripheral is serial port.
The machine supports only MIPS32 CPUs.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In barebox we used 1MiB sections to map our SDRAM cachable. This
has the drawback that we have to map our sdram twice: cached for
normal sdram and uncached for DMA operations. As address space gets
sparse on newer systems we are sometines unable to find a suitably
big enough area for the dma coherent space.
This patch changes the MMU code to use second level page tables.
With it we can implement dma_alloc_coherent as normal malloc, we
just have to remap the allocated area uncached afterwards and map
it cached again after free().
This makes arm_create_section(), setup_dma_coherent() and mmu_enable()
noops.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The new MMU setup will need SDRAM base addresses and sizes.
For this reason convert the MMU enabled ARM boards:
- move mem setup to mem_initcall. This is early but
still makes sure that we already have the console available
- move MMU setup in this initcall temporary as after the mmu_init will generic
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
We want to use the memory banks later in the MMU which is
independent of Linux, so move this to a location which is
always compiled.
Also, make the memory bank list global and add an iterator
for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
use generic read/write depending on the memory size
if no reg_read/write defined
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
...and update all users. The header file can be used on mx51 and mx53.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The register based fuse readout is not available on i.MX27/31
SoCs, so make explicit sensing the default.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Do not depend on the specific SoCs for the IIM module, but
instead exclude the one that don't have this unit.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The IIM module uses two drivers, one for the general IIM
module and one for the individual banks.
This patch turns this into a single driver to ease registration
of the resources. This changes the user visible behaviour in
the way that the explicit_sense_enable and permanent_write_enable
device parameters are no longer bank specific but for the
whole device. Also, the IIM module supports a maximum of
8 fuse banks, with these patch all of them are registered, even
if they are not present in a SoC.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
pass the hccr and hcor register base via resource
instroduce add_generic_usb_echi_device with hccr = base + 0x100 and
hcor = base + 0x140
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This patch adds resources for the Altera TSE driver as
this driver has been moved to resources usage.
The serial device also uses resources declared with the helps
of add_generic_device.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a helper function for boards to register their memory
devices. This makes the board code smaller and also helps
getting rid of map_base and struct memory_platform_data.
And switch all of the memory to it
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
we keep struct memory_platform_data for now on we will switch off the memories
resources to struct resource
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)
so we will match the erase block size
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Patrice Vilchez <patrice.vilchez@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix an error when bootm support is not choosen during
the configuration.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When the bus_width was set to 8, then only one data-line has been initialized.
Signed-off-by: Hubert Feurstein <h.feurstein@gmail.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
MLO is to big (>40000) to save Space disable CONFIG_FS_RAMFS and
CONFIG_FS_DEVFS in defconfig
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If we are using barebox on a NiosII/e variant, the
mul instruction is not supported and causes an exception.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If booting from NAND GPMC_IRQ_ENABLE is not cleared, causing crash if kernel
request the gpmc irq. gpmc_generic_init clears GPMC_IRQ_ENABLE
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Heavily based on original Juergen Beisert's code.
Signed-off-by: Alexey Galakhov <agalakhov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The flush_dcache_range function takes an absolute end address
so we have to add start address to the second parameter.
Signed-off-by: Franck JULLIEN <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In order to match the example I'll provide on my website,
set the system frequency to 100MHz in the generic board
nios_sopc.h
Signed-off-by: Franck JULLIEN <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The device init function has the name of one of my board (comBoard).
This patch fix the name of the function to generic_device_init.
Signed-off-by: Franck JULLIEN <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds kernel_loc, kernelimage_type and bootargs to the
generic board environment. This allows the generic board
to boot linux on the example I'll provide on my website.
Signed-off-by: Franck JULLIEN <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is useful to detect a barebox image and to be able
to copy only the image size if barebox is stored on
raw partitions which are bigger than the image.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix following warning:
arch/arm/boards/karo-tx25/lowlevel.c: In function 'board_init_lowlevel':
arch/arm/boards/karo-tx25/lowlevel.c:75:6: warning: unused variable 'i'
Signed-off-by: Marek Belisko <marek.belisko@open-nandra.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix following warning:
arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c: In function 'eukrea_cpuimx35_devices_init':
arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c:176:15: warning: unused variable 'tmp'
Signed-off-by: Marek Belisko <marek.belisko@open-nandra.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds the bootm support to the Nios2 arch.
Signed-off-by: Franck JULLIEN <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The PHY address must be passed to the driver via platform_data.
Signed-off-by: Franck JULLIEN <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If OMAP4 fall back to MMC1 boot in bootmode 0x39 (NAND,USB,UART,MMC1)
NAND and MMC bit in TRACING_VECTOR3 are set. With changed order it will
detect boot from MMC.
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add some common xload helper functions to determine the boot source
on omap3/4 and to load images from mmc and nand.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On several boards without MMU support the vectors cannot be mapped
to 0x0 and exception support is nonfunctional anyway, so make this
configurable.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds BCH ecc support to the omap nand driver. The BCH
error correction allows for up to 8 bit error correction. It is
also needed for booting from nand on omap4.
This is based on code from Sukumar Ghorai <s-ghorai@ti.com>:
[PATCH] omap3: nand: bch ecc support added
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On omap we use different ecc modes for different purposes. The initial
boot code has to be written with hardware ecc whereas Linux usually uses
software ecc. To be able to write in both modes with a sinlge barebox
image introduce a eccmode device parameter.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If compiled without gpio support the linker will throw the
gpio functions away anyway, so make the omap kconfig entries
a bit easier.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Give this omap specific entry an omap namespace. Also, remove
unnecessary dependency to omap2/3 in nand Kconfig.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The original plan was to add all omap devices into the boards/omap
directory. Anyway, there will be reasons to put a board somewhere
else, so move the generic parts into the omap architecture directory.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current gpio support is derived from the kernel which allows
for support for omap2/3/4 in a single kernel. We do not need this
here, so make it more simple to be able to add omap4 support later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When booting from NAND, its important to know the correct page size. When
the NAND is used as the boot source, four dedicated pins are used to configure
the correct page size and address cycles. These pins can be read back in one
of the NFC registers to parametrize the load function.
This patch also extends the read routine to support more than four address
cycles on demand.
BTW: At least some mini2440s are misconfigured to use five address cycles for
a NAND device that is known to need only four address cycles. In this case the
vendor is at our side: This NAND simply ignores any additional address cycles
than required.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Teresa Gámez
Sascha Hauer
shc@milas.spb.ru
Jean-Christophe PLAGNIOL-VILLARD
Antony Pavlov
Marc Kleine-Budde
Andre Naujoks
Franck Jullien
Hubert Feurstein
Jan Weitzel
Alexey Galakhov
Peter Korsgaard
Marek Belisko
Thomas Mayer
Juergen Beisert