The configuration for NAND has been aligned with values
from U-Boot and completed with TIMINGS initialization
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
MODE register has offset 0x10 and at offset 0x0C there is
a TIMINGS register.
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs.
Besides the functional driver itself, it also adds SoC specific PHY
setup required for PCIe. Currently, only Armada 370 is fully supported.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Accessing MBUS windows not backed-up by e.g. PCIe devices will
hang the SoC. Disable MBUS error propagation back to CPU allows
to read 0xffffffff instead of hanging the SoC.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM946E-S is used in the DIGIC family SoCs.
ARM946E-S core supports ARMv5TE and has Cache & MPU.
Linux kernel uses ARMv4 MPU cache routines for ARM946E-S core.
E.g. see linux.git/boot/compressed/head.S:
.word 0x41009400 @ ARM94x
.word 0xff00ff00
W(b) __armv4_mpu_cache_on
W(b) __armv4_mpu_cache_off
W(b) __armv4_mpu_cache_flush
So select CPU_32v4T for ARM946E-S despite of ARMv5TE support.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On at91sam9n12 soc, it has pllb, while on sama5d3 soc,
it doesn't has pllb.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is a limited board support for the Freescale P1010RDB.
The board boots from NOR and output the prompt to the serial port
at 115200 bauds. All 3 Ethernet ports are supported by the gianfar
driver. I2C devices are accessible on both bus and the memory is
initialised by the 85xx DDR driver.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support for the Freescale P1010 including errata for this CPU,
SoC frequency calculation and GPIO settings.
The mpc85xx configuration options file is re-ordered to facilitate
board option selection.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a minimal Integrated Flash Controller header file and new
definitions to support the P1010 SOC.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Move the configuration, control and status register base address
(CCSRBAR) relocation to the start-up processing. This addresses
TLB faults found during testing on the Freescale P1010RDB and
also matches the current U-Boot functionality.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On Marvell MVEBU SoCs memory size is set up by BootROM and can be read
from SoC's RAM controller. With early DT fixups available, set corresponding
DT node to reflect accessible amount of directly attached RAM.
This patch also removes non-DT call to arm_add_mem_device to silence a
warning about request_region conflict due to adding a mem device twice.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With proper DT fixup in place, we can now remove the overwrite of
mbus ranges in Armada 370 Mirabox and Armada XP Openblocks AX3.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For each supported MVEBU SoC, add the corresponding remapped registers
to fix them up in provided DTBs.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Device trees can be passed by primary boot loader or appended to
barebox binary. Unfortunately, before probing devices from such
a device tree, no fixup can be applied.
Add a call to of_fix_tree() right before probing devices to catch
some very early fixups.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Allocate space for the resulting image (FCB+DBBT+Firmware) in
imx_bbu_internal_v2_write_nand_dbbt() instead of its caller to make the
code simpler.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead oof using the same constants multiple times use a variable
to make the meaning of the constants clear.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Documentation clearly states that the FCB at offset 0x68 has
to contain the start page of the firmware. In our case this
was set to 0x0. I don't know how this could ever work, but it
did, at least until:
15ee301 ARM: i.MX: bbu-internal: optionally use DCD data from image
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We have the hardcoded value 0x8000 for the space needed for FCB and
DBBT in several places. Use a variable instead and initialize it
correctly with 12 * meminfo.writesize (which is in fact 0x6000 for
2k pagesize).
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a pinctrl driver for pin muxing on Marvell Armada XP. The
driver is ported from Linux and modified to fit on Barebox's common
mvebu pinctrl driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a pinctrl driver for pin muxing on Marvell Armada 370. The
driver is ported from Linux and modified to fit on Barebox's common
mvebu pinctrl driver.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We need to flush out the ttb in order to make the
changes observable to the page walker.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Compiling the tree with allyesconfig is helpful because different
compilers (gcc, clang) or static checkers (e.g. clang's scan-build)
can then process and check more code.
This patch introduces two new configuration symbols that Kconfig files
can depend on. That way, code that is only working where a cache or DMA
implementation exists can be opted out.
Signed-off-by: Holger Schurig <holgerschurig@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Android image format makes the same mistake as the U-Boot uImage
format: It makes the load address mandatory. In a way it is even worse
since the 'fastboot' host tool thinks that 0x10000000 is a good default
when no address has been specified on the command line.
Instead of only relying on the Kernel load address in the image try
to automatically find a good base address when requesting the addresses
from the image failed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This increases the malloc to half of the available memory in a
bank. This helps with some usecases requiring a lot of memory.
The other half is still available as scratch area and for
putting the kernel binary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Many boards use a USB vendor id of 0x4321. This doesn't exist and
shouldn't be used. Remove this and also the bogus product id of 0x1234.
The boards will use the barebox default vendor/product id then.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This renames USB to USB_HOST since this is what the symbol really
means. Introduce a USB symbol which is selected by both USB_GADGET
and USB_HOST. This gives us a symbol to let common USB code depend
on.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
On the i.MX53 this has the effect that in early init only
half of the memory bank is detected and the barebox image
is place in the middle of SDRAM.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ppc implementation is identical to the generic implementation, so
use the generic one instead.
Also add the missing __ffs function.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We have many variants of the same bitops.h file. Consistently
use the same file for all architectures which completely use
the generic bitops versions.
Some architectures had static inline versions of functions
identically to the generic versions, these are removed and
the generic versions are used directly now.
Also several architectures depend on the generic find_*_bit
functions but didn't have the GENERIC_FIND_NEXT_BIT Kconfig
option selected. This is added where needed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This will add support for Embedsky E9 board.
It is a small board based on i.MX6 Quad with 2G of RAM.
http://en.embedsky.com/product_info.php?cateid=169&id=169
Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
use in devinfo Protocols
Tested today on qemu with all the GUID translated
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
phyFLEX boards beginning with 1362.2 have a workaround for this
i.MX6 bug:
ERR006282 ROM code uses nonreset PFDs to generate clocks, which may
lead to random boot failures
On these boards the SD4_DAT3 pin os connected to the CMIC. The CMIC
will reset the board after 10s when the pin isn't toggled.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The rule in barebox is to name the directories after
the modules. As hummingboard is just one of the
carriers for the MicroSOM module, name the directory
accordingly.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of repeating the same lowlevel init for every board
move it to it's own initcall.
Avoids code bloat and shaves off almost 1.5kB of uncompressed
barebox size for a default imx_v7_defconfig build.
For boards wherethe hostname setup was done in the postcore
initcall we move this to a device initcall to get it out of
the way.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix only two "interupt" misspellings in entire barebox codebase.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix misspellings of "persistent", including the renaming of a function
to "register_persistant_environment".
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add new chip revisions for the new tap-out TO1.5 (i.MX6Q/D) and TO1.2
(i.MX6DL/S)
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For some phyFLEX-i.MX6 modules the call __barebox_arm_head() was not removed.
With this function the barebox does not start.
Signed-off-by: Christian Hemp <christian.hemp@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The functions are already in the sandbox, just the #defines are
missing.
Signed-off-by: Holger Schurig <holgerschurig@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The doxygen documentation is long outdated. Remove it. It will
be replaced with sphinx based documentation later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Enables all relevant errata workarounds for the
i.MX6 SoC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Header only implementation, so they can be pulled
into the individual SoC cpu init functions.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds pinctrl drivers for Marvell Dove and Kirkwood SoCs based
on a common driver stub. This design is based on the corresponding
Linux driver and should ease additional drivers for Marvell Armada
SoCs.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We already have 'select COMMON_CLK' so 'select HAVE_CLK'
is redundant.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Marvell MVEBU SoC id and revision can be read out from any PCIe port
registers. This adds corresponding code to read out id and revision
and provides a helper function for drivers to use it.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Marvell MVEBU DT files contain some nodes mapped to PCI address space,
add the translator Kconfig to be able to iomap those node's addresses.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Also we can enable m24c02 eeprom chip in dts-file e.g.
&i2c0 {
status = "okay";
eeprom: m24c02@50 {
compatible = "spd";
reg = <0x50>;
};
};
Alas! qemu mips malta spd m24c02 eeprom chip emulation is not perfect:
the block read operation does not work properly.
Here is an example.
If we read eeprom content byte-by-byte then there is no problem:
barebox:/ for i in 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f ;
> do i2c_read -b 0 -a 0x50 -r $i -c 1 ; done
0x01
0x75
0x54
0x00
0x82
0x08
0x00
0x01
Compare this output with content of qemu.git/hw/mips/mips_malta.c:
static eeprom24c0x_t spd_eeprom = {
.contents = {
...
/* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
But if we read several bytes at once the we have data corruption:
barebox:/ i2c_read -b 0 -a 0x50 -r 0x8 -c 8
0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
MULTI_PBL images have a built-in dtb by default. With all MVEBU
SoCs converted to MULTI_PBL images, get rid of the extra Makefile
rules for appended dtbs.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
With all SoCs converted to DT based probing, select
PBL_MULTI_IMAGES support and get rid of SoCs Kconfig
choice to allow multiple boards to be selected.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This converts Marvell Armada XP based PlatHome Openblocks AX3-4
to PBL_MULTI_IMAGES. A DT overlay is added to keep possible
barebox-specific changes separated and added to lowlevel
board init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This converts Marvell Armada XP based Marvell Armada XP GP
to PBL_MULTI_IMAGES. A DT overlay is added to keep possible
barebox-specific changes separated and added to lowlevel
board init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This converts Marvell Armada 370 based Globalscale Mirabox
to PBL_MULTI_IMAGES. A DT overlay is added to keep possible
barebox-specific changes separated and added to lowlevel
board init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
With Armada 370/XP DT files available, convert Armada 370/XP SoC init
to register basic devices from DT only. Makefile targets for dtbs will
be removed again as soon as MULTI_PBL is available.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
With Kirkwood DT files available, convert Kirkwood SoC init
to register basic devices from DT only. Makefile targets for
dtbs will be removed again as soon as MULTI_PBL is available.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Armada XP timers can be run from a 25MHz fixed clock. Add the corrsponding
clock and clock alias to SoC setup.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
mach-mvebu has two files containing lowlevel code. Consolidate both into
mach-mvebu/lowlevel.c. Also put the now empty mach-mvebu/common.c into
non-lowlevel obj-y as it will be used for common non-lowlevel code later.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
All current boards use the same TEXT_BASE, therefore set the default
TEXT_BASE by SoC instead of by board.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
For i.MX devicetree boards the console= parameter is automatically
generated and can be dropped from the env files. If a file becomes
empty then, remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The arch/arm/include/asm/gpio.h header file contains
#ifndef CONFIG_GPIOLIB
#include <mach/gpio.h>
#else
#include <asm-generic/gpio.h>
#endif
We use CONFIG_GPIOLIB=y for the only mach-versatile
Versatile/PB board so there is no need of <mach/gpio.h>.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The bootargs are now autogenerated by barebox and the hostname should
not be preconfigured.
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Commit 0d6392de4a introduced a stripped
down device tree used for both white and black Beaglebone variants
that included the 256 MiB memory node from am335x-bone-common.dtsi.
This leads to the following error in the MLO:
mmu: Critical Error: Can't request SDRAM region for ttb at 9fff4000
This patch removes the (for the Beaglebone black) invalid memory size
from the common device tree and instead registers the memory bank
manually in the board file.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
External NOR boot only requires copying the image to NOR Flash.
This also adds (un)protecting the flash which is required for
NOR Flash.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Register the board specific environment during runtime using
defaultenv_append_directory() to make it available for multi
image support.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We used to relocate the executable to the current address. This does
not work when the executable runs from a readonly location like for
example NOR Flash. Test if we run from inside the available memory and
if we do, relocate to the current address as before. Otherwise copy
the executable to the start of memory and relocate to that address.
While at it add some comments to the code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch removes non-DT support for PCM-038/PCM-970 and switch
to devicetree probe for these targets.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add intermediate .S files to .SECONDARY. Otherwise make deletes them
and regenerates them each build.
Also remove KBUILD_DTBS since the make system descends in dts/ anyway.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The FSF address has changed; The FSF site says that
address is
Free Software Foundation
51 Franklin Street, Fifth Floor
Boston, MA 02110-1301
USA
(see http://www.fsf.org/about/contact/)
Instead of updating it each time the address changes,
just drop it completely treewide.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The beaglebone white and black have different devicetrees. Both
get linked into the MLO which makes it too big. Use a devicetree
generated from am335x-bone-common.dtsi which both board variants
can share. This reduces the binary size by about 30k.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fixes:
arch/ppc/boards/freescale-p1022ds/ddr.c: In function 'fsl_ddr_board_info':
arch/ppc/boards/freescale-p1022ds/ddr.c:39:21: warning: assignment discards 'const' qualifier from pointer target type [enabled by default]
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fixes:
arch/mips/configs/dlink-dir-320_defconfig:52:warning: override: reassigning to symbol CMD_DHCP
arch/mips/configs/dlink-dir-320_defconfig:54:warning: override: reassigning to symbol CMD_PING
arch/mips/configs/dlink-dir-320_defconfig:55:warning: override: reassigning to symbol CMD_TFTP
arch/mips/configs/dlink-dir-320_defconfig:64:warning: override: reassigning to symbol FS_TFTP
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fixes:
arch/arm/configs/friendlyarm_mini2440_defconfig:38:warning: override: reassigning to symbol CMD_TFTP
arch/arm/configs/friendlyarm_mini2440_defconfig:46:warning: override: reassigning to symbol FS_TFTP
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Mainly for Jetson TK1 support, but -next moved
some stuff around. Also enable some filesystems.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We can reuse the Tegra30 pinctrl driver, as the bit
layout is the same. Just add the pin and drivegroups
and some compile-time magic to avoid bloat.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If the bootloader doesn't init the architectural timer
on Cortex A15 Linux falls over when trying to boot.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
I don't know why get_runtime_offset fails on T124 yet,
but this is a safe workaround, with the nice side-effect
of fixing second stage barebox loading.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Don't disable clk to unrelated devices in the process.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Those 3 are needed to power CPU0 from the CPUG cluster.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Even the lowlevel functions are growing to a
size where having a stack seem beneficial.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
In RCM aka recovery mode the BootROM waits for a
usbloader to take over control. On most boards this
is triggered by holding a physical switch which may
be inconvinient at times. Add a command to switch
into RCM from software.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
It wasn't hard to find the right spot to copy the image
to before, but this makes it a bit more explicit.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The voltage for programming the fuses is external to the SoC and
on some boards this is controllable with a regulator, so add regulator
support to the iim driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Allow to read/write the registered MAC addresses in the iim
module directly via a device parameter.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX5 iim has an additional bit in the CCM module which
enables the supply. Add support for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
imx_iim_read is a iim internal function, so access the
internal functions rather than using the cdev API.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With devicetree devicenames start with numbers. Parameters on these
devices are not accessible since variables can't start with numbers.
Register a logical 'iim' device which makes the permanent_write_enable
and explicit_sense_enable parameters accessible again.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of duplicating data shared between the banks in a bank
specific struct, use a iim struct and a bank struct.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* fix indentation of options in 'help bootm'
* add missing help for -m
* put some output into debug/verbose mode
Signed-off-by: Holger Schurig <holgerschurig@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As stated in section 29.19.32 of SAMA5D3 Series datasheet, to move
from CS(n) to CS(n+1) the stride is 0x14 and not 0x10 as in the
other AT91 CPUs
Signed-off-by: Matteo Fortini <matteo.fortini@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The MB 77.07 is a small (80x80 mm) single-board computer
developed in Russia by the RC Module.
It was developed as an educational board for К1879ХБ1Я SoC
capabilities demonstration.
See http://www.module.ru/en/catalog/micro/micro_pc/ for details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit adds minimal support for the UEMD SoCs
from RC Module (http://www.module.ru).
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Use stdout-path instead of linux,stdout-path and use &uart format
instead of writing the full path.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
I assume I am the only person knowing that barebox is able to
merge devicetrees. This feature seems broken for a while now since
trying to merge devicetress results in:
unflatten: too many end nodes
Remove this feature to save the complexity.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Update cpuinfo to display the current CPU implementation
using the VR2 register defined in the architecture specification
v1.0
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The relocation code can now relocate from anywhere to
the RAM.
The old code assumed that the binary was copied to the RAM
by some PBL and then it just relocated the .text section
from the loaded address to the linked address.
Now, it first checks if vectors are somewhere else than the
linked address. If yes, there are copied to address 0 (or
to the exception vector base address if register EVBAR is
present).
Then, the .text section is relocated from its current location
to the RAM.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The OpenRISC architecture specification v1.0 defines
new SPR registers. This patch adds registers definition
for group 0 and update bit definitions for the CPU
configuration register.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The ARM pbl is linked at (TEXT_BASE - SZ_2M). This conflicts with the temporary
stack used in s3c24x0_nand_boot. Moving the stack to (TEXT_BASE - SZ_2M) fixes
this problem. With this patch a compressed barebox with pbl can boot on
mini2440 from NAND.
Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Matteo Fortini
Antony Pavlov
Sebastian Hesselbarth
Bo Shen
Renaud Barbier
Sascha Hauer
Lucas Stach
basti@linux-source.de
Holger Schurig
Andrey Panov
Jean-Christophe PLAGNIOL-VILLARD
Teresa Gámez
Robert P. J. Day
Lucas Stach
Christian Hemp
Christian Hemp
Jan Luebbe
Philipp Zabel
Alexander Shiyan
Bo Shen
Franck Jullien
Michael Olbrich
Silvio Fricke
Wadim Egorov