This driver is dts-only version of driver from Linux v3.14-rc5.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit adds minimal support for the DaVinci DM365 SoCs
from Texas Instruments.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This macros are used in exported from linux TI DaVinci code.
Also this macros are used in MIPS cache support code.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For memory reaching the end of the address space
phys + bank->size overflows to 0. Fix this by right shifting
phys and bank->size before adding them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Sean Cross <xobs@kosagi.com>
- If we have no memory registered in mmu_init() it's a critical bug.
panic in this case.
- If we do not have a ttb when dma_alloc_coherent or remap_range is
called it's also a critical bug. Panic in this case.
- if find_pte is called with an address outside our memory banks dump
the memory banks and the address to give more clue what went wrong.
Also add some hints what might went wrong to the code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To ease DT import from Linux, which is still maintained in-tree, we
separate barebox-specific changes by including the original dts in
a separate DT file. This allows to overlay modifications and keep
clean DT history. Additionally, this patch updates i.MX27 DTS tree.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The commit
ARM: Make ENTRY_FUNCTION more robust
changed the behaviour of the ENTRY_FUNCTION. For the Socrates the call to
__barebox_arm_head() was not removed. Do so now otherwise the Socrates will
not be able to boot barebox.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- enable more commands :
(menu, password, loadb, let, mm, sha*, bootz, of*, memtest)
- enable led and led triggers
- enable sata support
- enable USB chipidea support
- enable USB network drivers
- enable NFS and DNS support
- enable EXT4 support
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tested on i.MX53 START-R :
barebox@Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
imx-sata 10000000.sata: port 0: SATA link ok
imx-sata 10000000.sata: port 0: Spinning up device...
imx-sata 10000000.sata: port 0: ok.
ata0: registered /dev/ata0
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- declare the rigth mux for the GPIO used to enable the USB's 5V
- enable USB host controller
tested on i.MX53 START-R :
barebox@Freescale i.MX53 Quick Start-R Board:/ usb -f
USB: scanning bus for devices...
Bus 001 Device 001: ID 0000:0000 EHCI Host Controller
Using index 0 for the new disk
Bus 002 Device 003: ID 0951:1654 DT R500
Bus 002 Device 002: ID 0000:0000 EHCI Host Controller
3 USB Device(s) found
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
I accidently merged the initial data device node which contained
clocks in the sata node which were not compatible to the ones
in the kernel. Fix this.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The mx31moboard is used on the marXbot, Eyebot and Footbot robot.
Signed-off-by: Philippe Rétornaz <philippe.retornaz@epfl.ch>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Enable memtest, MMU and iomem support on the P2020RDB and DA923RC.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add support to enable caching on a memory region during the memory test.
Tested on P2020RDB and DA923RC.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Memory regions on MPC85xx boards are incorrectly defined leading to
corruption when running memory tests. This patch updates the memory
layout of MPC85xx boards so that critical memory regions can be
correctly reserved during the memory test.
Tested on the P2020RDB and DA923RC.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We can compile barebox for multiple boards at once, but currently
they all share a single default environment. This patch adds a
defaultenv_append() which boards can call to customize the default
environment during runtime. Each board now generate default environment
snippets using bbenv-y and add them during runtime with defaultenv_append()
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When booting from SD Card we don't want to load an env
from EMMC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This is a squashed commit of the following downstream
commits:
- Set CS0_END in MMDC0_MDASP to 32Gb (4GB)T
- Fix writes to MMDC0_MDSCR
- Enable bank interleaving (BI_ON) and set write
additional latency (WALAT) to 1 cycle in MMDC0_MDMISC
- Set ARCR_DYN_JMP=1 and ARCR_DYN_MAX=15 in MMDC0_MAARCR
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This was broken with commit 2a1f5f802e
"ARM: rename boards to more consistent naming"
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Sets up MSELECT to let main CPUs talk to peripheral devices and starts
high performance A9 CPU cluster.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Allows to talk to external PMIC devices to bring up CPU rail.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch gates the clocks to GPU, IPU, and VPU units by default,
significantly reducing the VDDSOC power draw while barebox is running.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
SYSCON3 register is not used in the barebox, so remove driver for
this register entirely.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Most devices relevant for barebox like sd/emmc/network/uarts
work. Devicetree contains several undefined drive strength settings,
these can be fixed once the kernel has sorted this out.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Adding minimal support for the UDOO board.
For more information about the board: http://www.udoo.org/
Signed-off-by: Raphael Poggi <poggi.raph@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For proper startup we need to give clocks and IO signals some time to
stabilize. Tegra2 got away without them, but Tegra3 seems to be a bit
pickier.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Lowlevel code runs when not relocated yet, so we have to make extra sure
not to emit jump-tables with absolute adresses when evaluating switch
statements.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For computer modules the naming standard is to have
a single board directory named after the module and
have all the baseboard support beneath it.
Also change the CONFIG name, as we may want to build
all the baseboards at once.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fix the chip select configuration register offset increment and summing
of bank size so that, for chip select index greater than 0, barebox can
determine the total memory size from enabled banks.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- Make sure the LCDC ipg clock is turned off during startup
- register all LCDC clocks (ahb, ipg, per) and pass them to driver
This is necessary because the LCDC doesn't have an enable bit. It just
starts working once the clocks are turned on. If the registers have
invalid values at that time the controller goes into some error state.
So we have to make sure the clocks are turned off during startup and
only turned on in the driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tested on i.MX53 START-R :
barebox@Freescale i.MX53 Quick Start-R Board:/ ata0.probe=1
imx-sata 10000000.sata: port 0: SATA link ok
imx-sata 10000000.sata: port 0: Spinning up device...
imx-sata 10000000.sata: port 0: ok.
ata0: registered /dev/ata0
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
tested on i.MX53 START-R :
barebox@Freescale i.MX53 Quick Start-R Board:/ usb -f
USB: scanning bus for devices...
Using index 0 for the new disk
Bus 001 Device 002: ID 0951:1654 DT R500
Bus 001 Device 001: ID 0000:0000 EHCI Host Controller
Bus 002 Device 003: ID 0000:0000 EHCI Host Controller
3 USB Device(s) found
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- declare the rigth mux for the GPIO used to enable the USB's 5V
- enable USB host controller
tested on i.MX53 START-R :
barebox@Freescale i.MX53 Quick Start-R Board:/ usb -f
USB: scanning bus for devices...
Bus 001 Device 001: ID 0000:0000 EHCI Host Controller
Using index 0 for the new disk
Bus 002 Device 003: ID 0951:1654 DT R500
Bus 002 Device 002: ID 0000:0000 EHCI Host Controller
3 USB Device(s) found
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- configure the MC34708 properly so that USB can work
(the sequence is taken from u-boot)
- add the required defines to the mc13xxx include file
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This re-syncs Marvell Dove and Solidrun CuBox DT files with current
files from Linux v3.14. Since barebox specific properties are now
kept separated, we don't need to tweak them anymore.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
To ease DT import from Linux, which is still maintained in-tree, we
separate barebox-specific changes by including the original dts in
a separate DT file. This allows to overlay modifications and keep
clean DT history.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This imports the Marvell mbus driver from Linux. The mbus is the
main downstream bus found on all Marvell Orion SoCs. The driver
deals with re-configurable address windows which are currently
parsed from DT. Also enable the driver as default on all MVEBU
SoCs. While at it, also reorder drivers/bus/{Kconfig,Makefile}
alphabetically.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Similar to mount(8) the barebox command mount now supports passing a string
to the file system driver via -o.
This is used in the next commit to let the user specify port numbers for
nfs mounts.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This allows to load all the lowlevel init code, including the
uncompressor, inside SRAM and not just the bare init part. This is
useful when pbl is used as a first-stage bootloader but is loaded by an
external firmware.
Signed-off-by: David Vincent <freesilicon@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Increase the malloc size so that larger debug Linux image can be loaded.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
A boot script is added to load DTB and Linux images for booting.
The init script starts the boot script after a 5s timeout window.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This renames the Freescale and Phytec board directories and defconfig
files to a common naming scheme. The board directories are named
<vendor>-<board> and the defconfig files are named
<vendor>-<board>_defconfig. Also the DataModul realq7 is renamed to its
Marketing Name eDM-QMX6.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Some boards need gpio functions very early and also sometimes
is useful to toggle gpios during early code debug. This adds a header
file for setting i.MX gpios early.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Which bootmode is selected has no longer to be chosen by Kconfig. The
boards can decide themselves which bootmode they want to support. This
makes it unnecesary to ask the user which bootmode shall be supported,
so the "Select boot mode" becomes invisible and both support will be
compiled in as needed by the boards. NAND_IMX_BOOT goes away and the
already existing ARCH_IMX_EXTERNAL_BOOT_NAND can now be used for the
boards to depend on external nand boot.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Only one GPT will be used, but with devicetree support we can't predict
which one it is, so we need the clock lookup for all GPTs to ensure
that the timer gets its clock.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If we are running from NFC SRAM and we are passed boarddata
containing a devicetree pointer then it point to an address relative
to the NFC SRAM start. First thing we do is to copy the initial
binary to SDRAM and jump there. The devicetree pointer has to be
adjusted by this offset.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When compiling with multiimage support ld_var(_barebox_image_size) only
contains the length of the PBL image, but not including the appended
compressed data. With this patch the image size is read from the barebox
header instead which contains the correct size, either from the linker
or from the fix_size tool.
This makes the external_nand_boot compatible with multiimage support.
Tested on Phytec phyCARD-i.MX27 with and without PBL.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Instead of passing the offset to the fix_size tool check the image to
fixup for a valid header so that only recognized files are fixed up.
This makes the usage of this tool safer.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
on the edmqmx6 barebox is loaded into SRAM, so it must not get
too big. Disable some stuff to make the image fit into SRAM again.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
barebox only recognizes boarddata as dtb if it is inside SDRAM, so
copy the dtb there if necessary.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The UBI/UBIFS support is enabled and a script is added to attach
the UBI device and mount the UBIFS partition. This allows the loading
of firmware images from the NOR flash.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Removed the ppc bit operation functions and definitions in the ppc
file asm/bitops.h since these are already defined in the asm-generic header
files. Moved ffs64 definition to the mpc85xx header files because
the function requires the inclusion of linux/log2.h which also includes
asm/bitops.h.
The conflict was noted when UBIFS was enabled in barebox.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Expression (pdimm->data_width >= 32) || (pdimm->data_width <= 40)
always evaluates to true, so probably we need to use "&&" here.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- add chosen node with
- environment
- linux,stdout-path
- add dsr value to eMMC
- add provide-mac-address property to iim node
- set memory size in memory node to 0 since we have two different
memory sizes which have to be handled.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With multiple instances we returned -EBUSY which will provoke a
log message. Return successful instead since the i.MX27 has multiple
GPTs in the devicetree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With multiboard support the cpu_is_* macros are no longer compile time
generated and do not work in early code, so pass a v1 variable around.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We used to copy the initial binary portion from NFC SRAM to TEXT_BASE
and jumped there. With relocatable PBL TEXT_BASE becomes 0, so this
doesn't work. This is changed to copy the initial binary portion
to the beginning of SDRAM instead.
Tested on Phytec phyCARD-i.MX27 and Karo TX25 with and without
relocatable pbl.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
BUG() uses printf which is not available in pbl, so do not use it here.
This becomes necessary when multiple CPU architectures are compiled in.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The cache-v7 code uses assembler instructions which do not
exist on before v7, so explicitely pass armv7-a to this file
to make the compiler happy.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
default_environment_path only exists when CONFIG_ENV_HANDLING is enabled.
Boards would have to #ifdef this if they wanted to use
default_environment_path. Use accessor functions instead which can
be ifdeffed on a single place.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch updates the CLPS711X UART driver.
The update adds support for use with devicetree and
makes driver comatible with current driver from kernel.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
No reason to make SYSCON driver name unique to that processor.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This enables a lot of new features in the defconfig:
- Image compression
- FAT support
- Ext4 support
- UBIFS support
- more commands
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The MPLL can be driven from the low frequency reference clock. This
is the reset default. Currently the clock code assumes this has been
changed from the lowlevel code. If that didn't happen we get wrong
clock rates. This adds the missing clocks so that we get correct
clock rates.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The entry function wasn't changed properly when the
prototype changed.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The start-r QSB has a different pmic than the older start QSB.
Add a new dts for the QSRB and let barebox generate two images when
LOCO is selected.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
There are two versions of the i.MX53 LOCO:
- the MCIMX53-START board
- the MCIMX53-START-R board
The MCIMX53-START-R has a mc34708 pmic and is otherwise the similar to the
MCIMX53-START. To prepare for the START-R, move all common nodes to a new
imx53-qsb-common.dtsi
and remove everything but the board name and pmic from the imx53-qsb.dts.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Solidrun has renamed the Carrier-1 to Hummingboard.
This is also the name that is used in upstream Linux,
change barebox to be in line with that.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Only the 1GB variant is supported for now, as I don't
have anything other to test with.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Needed to be able to update other i.MX 6 DTs properly.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Otherwise we end up doing the VMX53 board init for
unrelated boards when using a multiimage build.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds support for new board variants. Now Supported are:
- i.MX6q module with 1GiB Micron RAM
- i.MX6d/q modules with 1GiB/2GiB Nanya RAM
- i.MX6s modules with 512MiB/1GiB Nanya RAM
This has been tested on:
- i.MX6q module with 1GiB Micron RAM
- i.MX6d module with 2GiB Nanya RAM
- i.MX6s module with 1GiB Nanya RAM
The possible RAM equipment is:
- For the 512MiB module: 2x Nanya nt5cb128m16fp-di
- For the 1GiB modules: 2x Nanya nt5cc256m16cp or 4x Micron MT41K128M16JT-125
- For the 2GiB module: 4x Nanya nt5cc256m16cp
The 512MiB Nanya board is assumed to work with the same DCD table
as the 1GiB Nanya board. The variant is detected by mirroring at
512MiB, but this hasn't been tested by Pengutronix.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This improves the initrd/devicetree placement in the bootm code.
We used to put the initrd at the start of the kernel + 8MiB. This
of course fails once the kernel gets bigger than 8MiB. Also the
place for the devicetree was allocated using malloc(). This can
lead to the problem that the devicetree is outside of the kernels
lowmem and thus not reachable for the kernel.
With this patch __do_bootm_linux gets a pointer to free space where
the devicetree and the initrd can be safely put.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The zImage should be placed where it won't be overwritten by the
uncompressed image, otherwise the kernel decompressing code has
to relocate the zImage before decompression. As Kernels tend to
become bigger put it into 32MiB into RAM if we have enough RAM
available.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is based on this linux commit:
commit 2fa36399e63c911134f28b6878aada9b395c4209
Author: Kelvin Cheung <keguang.zhang@gmail.com>
Date: Wed Jun 20 20:05:32 2012 +0100
MIPS: Add CPU support for Loongson1B
Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology
(ICT) and the Chinese Academy of Sciences (CAS), which implements the
MIPS32 release 2 instruction set.
[ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device
which also is why it identifies itself with the Legacy Vendor ID in the
PrID register. When applying the patch I shoveled some code around to
keep things in alphabetical order and avoid forward declarations.]
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Loongson (simplified Chinese: 龙芯; pinyin: Lóngxīn; literally: "Dragon Core")
is a family of general-purpose MIPS CPUs developed at the Institute of Computing
Technology (ICT), Chinese Academy of Sciences (CAS) in the People's Republic of China.
See http://en.wikipedia.org/wiki/Loongson for details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
When the board is on console, a way is added to manually power off the
board, on a long power key press (4s).
This enables to be able to poweroff the board whatever the state, and is
the only manual way (no mechanical possibility).
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As barebox has grown up in size, because UBI support is now embedded in
barebox, and because the IPL is at least rewritten to be fully GPL,
modify mioa701 support to take into account this new layout :
- IPL is version 0.5
- MTD layout is fully changed
- the boot sequence is rewritten :
- the volume up button triggers console mode
- upon PowerOn or Sleep exit, power key is debounced and if not
help board is powered off back
- sdcard environment override can now stop the autoboot sequence
- mtd environment override can now stop the autoboot sequence
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Update mioa701 board for new setup :
- double the barebox size to 524288 bytes
- add new commands
- add device tree support, for future PXA port to devicetree
- add reset source
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add the capability for the PXA architecture to poweroff.
As there is no true poweroff, ie. the power regulator is not available
for shut off from the core, the poweroff puts the SoC into a deep sleep
mode (mode 7), where almost no current is sunk.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Use PXA register RCSR to detect which is the reset cause. When
triggering a reset, clear the former reset source first.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As barebox has become the true SPL of mioa701 board (no intermediate
SPL), a bug was uncovered in the init procedure, where the CPU voltage
was to be increased by commanding the I2C voltage regulator, while the
I2C was shut down.
Fix it by unclock-gating the power I2C bus before using it.
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Import U-Boot start-up code from version git-9407c3fc to include the
latest CPUs errata and make future U-Boot code inclusion easier. The
code import is limited to the currently supported CPUs P2020/MPC8544.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The linker script and start up code are updated so that the bss
section is located above the barebox binary in memory. This removes
the reliance on a hard-coded value.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Updates to use a common linker script for all mpc85xx boards,
avoiding duplication.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
TLB support for the 85xx CPUs has been upgraded to support the MMUv2
page size definitions. This has been imported from U-Boot version
git-9407c3fc. This allows for future CPUs to make use of the new MMU
support.
Also the definition of MAX_MEM_MAPPED has been changed to avoid type
casting with "min" macro.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
all eMMC cards with DSR support used on different
revisions of TQMa53 needs the same DSR value.
just apply it.
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
having DSR support in mci-core we need a way to
forward the DSR value to the driver. Add it to
platform data for imx-esdhc
TODO: implement the same for other host controller
drivers
Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Using the ANATOP_SI_REV register we can only distinguish between
i.MX6q/d and i.MX6dl/s SoCs. Take the number of cores into account
to get the exact SoC type.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
__do_bootm_linux is called from the uImage, zImage and raw handlers.
In case of the zImage handler the kernel will already be loaded and
the kernel load code in __do_bootm_linux will do nothing. Move the
loading code to do_bootm_linux so that __do_bootm_linux will always
be called with the kernel already loaded.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The common bootm code used to load uImage contents to SDRAM
before calling into the handlers if possible. This makes the
handlers complicated since they have to handle many cases. Instead,
introduce a helper to load the os after the handlers have figured
out a good load address.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This makes it possible to pull other DT changes from
the linux kernel repo. Plus it will make it possible
to slim down the i.MX6 dtbs at a later point.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reset GPIO now handled from DTS, no need to touch this in the board.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch includes update i.MX51 template and porting some barebox
DTS files to use new template.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Start a 2nd stage barebox with the Linux Kernel calling convention.
Right now barebox does not interpret ATAGs or devicetree passed
to it, but it doesn't hurt to pass parameters so that future bareboxes
can use them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As the place for the atags now is determined automatically the call
from the boards can be removed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
If a board does not specify a place for the atags list default to
SDRAM start + 0x100. The vast majority of boards uses this place
anyway, so the call to armlinux_set_bootparams() can be removed
for most boards.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
without "#ifndef __ASSEMBLY__ #endif", an assembly file
including this file will break compilation.
Signed-off-by: Du Huanpeng <u74147@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The IPU has a fractional pixelclock divider. When used, this produces
clock jitter which especially LVDS transceivers can't handle. Allow
to disable it via platform_data.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
With the IPU the way the display is connected is completely independent
of the framebuffer pixel format. So instead of specifying a pixel width
in platform_data we have to specify how the display is connected.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The OpenCores 10/100 Mbps ethernet MAC is often available on
OpenRISC-based SoCs and is supported by the OpenRISC architectural
simulator (or1ksim) as well.
The patch enables the driver on the 'generic' openrisc board.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
am33xx_register_ethaddr must be called before cpsw driver start.
Move it from devices_initcall to coredevice_initcall.
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
add compatible phytec,pcm051
clean up pinmux_emac_rmii1_pins
introduce davinci_mdio_default pin group
set AM33XX_MAC_MII_SEL via dts rmii-clock-ext
use bch8 as ecc mode
add pagesize to 24c32@52
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The Beaglebone and the AM335x Phytec phyCORE can be compiled
together, so merge the configs into a am335x_mlo_defconfig.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Storing the boot information in the image itself and passing a pointer
around between images is cumbersome and doesn't fit well with multiimage
support where the pointer we pass around is already occupied by the
devicetree.
Do the same as U-Boot does and store the boot information at the bottom
of the SRAM public stack.
To maintain the compatibility between new xloaders and older barebox
binaries we still pass the boot information to the next stage via pointer.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
barebox needs it to initialize the memory. While at it, give the
beabglebone black another name than the original beaglebone has.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As with devicetree support the binary will get too large for the
SRAM drop the configuration. It was mainly meant for debugging purposes
anyway.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This switches the am335x Phytec phyCORE to devicetree probe support.
For now we use a linked in dtb.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
An entry function should begin with a exception header. For this to work
properly the entry function should not contain any code which gcc might
put before the header. To make this sure change the ENTRY_FUNCTION macro
so that it generates one function which only contains the exception header
and a second function which contains the original body of the entry function.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The multi image startup process used to have three binaries involved:
- The lowlevel board code to initialize SDRAM
- the uncompressor
- the regular (compressed) barebox binary
Drop the uncompressor and put the uncompress code into the lowlevel
board code binary. This makes the startup process easier.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Update the IO configuration to the Quartus v13.1 version. This seems to fix a
stability issue under the linux kernel when started with barebox.
As this is undocumented, autogenerated stuff, one can not be sure what it really
does nor if it really fixes the problem or just relocates it.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This updates/changes the sdram config for the sockit to the quartus v13.1
autogenerated version.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The DTS file for MBa6x is imx6q-mba6x.dts, so it looks like this file
doesn't make any sense.
Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The definition if the FEC is used is made by the baseboard (MBa6x), not
by the module (TQMa6x). Move it there.
Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Use the new Quartus II v13.1 generated sequencer_defines.h file.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Quartus II v13.1 generates updated sequencer.[ch] files.
Integrate the changes into the current driver.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Running at 1GHz, rather than 13MHz certainly makes things a bit faster.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We run the system bus from the OSC clock during init, to avoid crashing
the system while reconfiguring the PLLs.
Switch to a more reasonable clock when we are done with this.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Before we jump to SDRAM where we just copied our code we have to
invalidate the instruction cache.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Currently unused in barebox, but useful for bootstrapping a tx25
from USB where a imx-image is needed.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds a devicetree-only driver for to configure the gpmc and its
child devices from dt. Currently only NAND is supported.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
- make debug messages more meaningful
- calculate value once and use it to print and configure instead
of calculating it twice
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
We want to check whether boarddata contains a valid dtb if it's inside
valid memory. This includes the base of SDRAM, so use '>=' instead of '>'.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Broken since:
| commit 72e561b5e8
| Author: Sascha Hauer <s.hauer@pengutronix.de>
| Date: Fri Jul 19 12:07:05 2013 +0200
|
| ARM: omap4: Use writel where appropriate
|
| Instead of making a pure 32bit write to a read/modify/write
| operation with sr32 use writel directly. This saves a few bytes
| of binary space.
|
| Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This introduces a single omap_init function which detects the
SoC and does all further SoC initialization. This is done to get
rid of initcalls without proper SoC protection. The same has been
done for i.MX already.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The omap3 and omap4/am33xx spi cores differ in the offset of the
registers in the address space. Instead of encoding this into the
resources use the platform_device_id mechanism. This is done in
preparation for devicetree probe support where the address space
is in the devicetree and can't be adjusted.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Since we use the generic ns16550 driver we need the regshift property
to correcty access the UART.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
For making #include <dt-bindings/...> work
We already have the necessary -I flag in dtc_cpp_flags, no nothing
needs to be done here.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The image will be named after the official name of this board:
barebox-freescale-mx6-sabreline.img
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Pull the board device reset GPIO pin high as this prevents
PCI bus probing.
The function da923rc_board_init_r is called at the postcore
initcall level so that the udelay function can take advantage
of the core initialisation.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The clock frequency property of the device tree node fsl,mpic is
added as it is needed by the PCI driver to function in newer
Linux version.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The current implementation of the bootloader specification depends on the
hardware name and the name of the device in /dev to match. As the default
hardware name is mciX and the device name is diskY the bootloader spec
cannot be used as is.
This patch implements a way to overwrite the device name similar to what is
possible for the imx-esdhc driver.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This adds an .oftables section right before .dtb section with
BAREBOX_CLK_TABLE to ARM linker script.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Due to unwind tables being generated by recent versions of gcc by
default, the x86 Barebox link fails with:
ld: section .eh_frame loaded at [00000000000197c4,000000000001f31f]
overlaps section .barebox_initcalls loaded at [00000000000197c4,0000000000019833]
Passing -fno-unwind-tables -fno-asynchronous-unwind-tables avoids this
problem.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
"%d" in format string requires a signed integer.
"%u" in format string requires a unsigned integer.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch provides a global cleanup barebox Kconfig files. This includes
replacing spaces to tabs, formatting in accordance format.
No functional changes.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
"%d" in format string requires a signed integer.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
asm/hardware.h does not have any content except including mach/hardware.h.
include mach/hardware.h directly where needed and get rid of asm/hardware.h
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
A lot of files rely on include/driver.h including include/of.h (and
this including include/errno.h. include the files explicitly so we can
eventually get rid of including of.h from driver.h
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add the Kconfig and Makefile directives to build barebox
for the GEIP DA923RC board.
Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Antony Pavlov
Sascha Hauer
Alexander Shiyan
Steffen Trumtrar
Eric Bénard
Philippe Rétornaz
Renaud Barbier
Uwe Kleine-König
Lucas Stach
Michael Olbrich
Philipp Zabel
Lucas Stach
张忠山
Raphaël POGGI
Sebastian Hesselbarth
David Vincent
Cristiano De Alti
Michael Grzeschik
Antony Pavlov
Robert Jarzmik
Markus Niebel
Jesús Guitarte
Du Huanpeng
Beniamino Galvani
Jan Weitzel
Robert Schwebel
Rostislav Lisovy
Vicente Bergas
Alexander Aring
Thomas Petazzoni